Hi Gerald,
On Fri, May 03 2024, Gerald Pfeifer wrote:
> Hi Martin,
>
> On Thu, 2 May 2024, Martin Jambor wrote:
>> + <li> GCC now supports AMD CPUs based on the znver5 core via
>> + <code>-march=znver5</code>. Based on ISA extensions enabled on
>> + a znver4 core, the switch further enables the AVXVNNI, MOVDIRI,
>> + MOVDIR64B, AVX512VP2INTERSECT, and PREFETCHI ISA extensions.
>
> just two small suggestions: We usually sort extensions alphabetically,
> so AVX512VP2INTERSECT, AVXVNNI, MOVDIR64B, MOVDIRI, and PREFETCHI. If
> there is a specific reason to do otherwise, that's okay of course.
>
> And I might write "In addition to the ISA extensions enabled on a znver4
> core, this switch..." to avoid the repetition of "based on" (and make it a
> bit more clear even that it is a full superset, not just 'loosely' based".
>
Thanks for the suggestions, I'll go ahead and commit the following then.
Martin
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 8dfbf7dc..46a0266d 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -954,6 +954,12 @@ __asm (".global __flmap_lock" "\n\t"
<code>-fsanitize=hwaddress</code> will enable <code>-mlam=u57</code>
by default.
</li>
+ <li> GCC now supports AMD CPUs based on the znver5 core via
+ <code>-march=znver5</code>. In addition to the ISA extensions
+ enabled on a znver4 core, this switch further enables the
+ AVX512VP2INTERSECT, AVXVNNI, MOVDIR64B, MOVDIRI, and PREFETCHI ISA
+ extensions.
+ </li>
</ul>
<h3 id="mcore">MCore</h3>
