On 5/6/24 3:42 PM, Vineet Gupta wrote:
On 5/6/24 13:40, Christoph Müllner wrote:
The combiner attempts to optimize a zero-extension of a logical right shift
using zero_extract. We already utilize this optimization for those cases
that result in a single instructions. Let's add a insn_and_split
pattern that also matches the generic case, where we can emit an
optimized sequence of a slli/srli.
...
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index d4676507b45..80cbecb78e8 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2792,6 +2792,36 @@ (define_insn "*lshrsi3_zero_extend_3"
[(set_attr "type" "shift")
(set_attr "mode" "SI")])
+;; Canonical form for a zero-extend of a logical right shift.
+;; Special cases are handled above.
+;; Skip for single-bit extraction (Zbs/XTheadBs) and th.extu (XTheadBb)
Dumb question: Why not for Zbs: Zb[abs] is going to be very common going
fwd and will end up being unused.
Zbs only handles single bit extractions. The pattern rejects that case
allowing the single bit patterns from bitmanip.md and thead.md to match
them.
Jeff
