Sure thing, see below PR.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013
Pan
From: Vladimir Makarov <vmaka...@redhat.com>
Sent: Thursday, May 9, 2024 8:21 PM
To: Li, Pan2 <pan2...@intel.com>; gcc-patches@gcc.gnu.org
Subject: Re: [pushed][PR114810][LRA]: Recognize alternatives with lack of
available registers for insn and demote them.
On 5/8/24 23:25, Li, Pan2 wrote:
Hi Vladimir,
Looks this patch results in some ICE in the rvv.exp of RISC-V backend, feel
free to ping me if more information is needed for reproducing.
========= Summary of gcc testsuite =========
| # of unexpected case / # of unique unexpected case
| gcc | g++ | gfortran |
rv64gcv/ lp64d/ medlow | 1061 / 69 | 0 / 0 | - |
make: *** [Makefile:1096: report-gcc-newlib] Error 1
Just pick one imm_loop_invariant-10.c as below.
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c:20:1:
error: unrecognizable insn:
(insn 265 0 0 (parallel [
(set (reg:RVVMF8QI 309 [239])
(unspec:RVVMF8QI [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))
(clobber (scratch:SI))
]) -1
(nil))
Thank you for reporting this. Could you fill a PR for this. I guess fixing
this might take some time.
