Ack, thanks Jeff and will fix it ASAP. Pan
-----Original Message----- From: Jeff Law <[email protected]> Sent: Tuesday, May 14, 2024 2:10 AM To: Li, Pan2 <[email protected]>; Kito Cheng <[email protected]>; [email protected] Cc: gcc-patches <[email protected]> Subject: Re: [PATCH v1] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar On 5/13/24 9:00 AM, Li, Pan2 wrote: > Committed, thanks Juzhe and Kito. Let's wait for a while before backport to > 14. Could you fix the formatting nits caught by the CI linter? === ERROR type #1: trailing operator (4 error(s)) === gcc/config/riscv/riscv-vector-builtins.cc:4641:39: if ((exts & RVV_REQUIRE_ELEN_FP_16) && gcc/config/riscv/riscv-vector-builtins.cc:4651:39: if ((exts & RVV_REQUIRE_ELEN_FP_32) && gcc/config/riscv/riscv-vector-builtins.cc:4661:39: if ((exts & RVV_REQUIRE_ELEN_FP_64) && gcc/config/riscv/riscv-vector-builtins.cc:4670:36: if ((exts & RVV_REQUIRE_ELEN_64) && The "&&" needs to come down to the next line, indented like if ((exts && RVV_REQUIRE_ELEN_FP_16) && !TARGET_VECTOR_.....) Ie, the "&&" indents just inside the first open paren. It looks like all the conditions in validate_instance_type_required_extensions need to be fixed in a similar manner. Given this is NFC, just post it for the archiver. No need to wait on review. Jeff
