Specifically the AND is masking off the upper 32 bits of the un-shifted value and there's an outer SIGN_EXTEND from SI to DI. However in the RTL it's working on the post-shifted value, so the constant is left shifted, so we have to account for that in the pattern's condition.
We can just drop the AND in this case. So instead we do a 64bit shift, then a sign extending ADD utilizing the low part of that 64bit shift result.
This has run through Ventana's CI as well as my own. I'll wait for it to run through the larger CI system before pushing.
Jeff
gcc/
* config/riscv/riscv.md: Add pattern for sign extended shift-add
sequence with a masked input.
gcc/testsuite
* gcc.target/riscv/shift-add-2.c: New test.
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 4d6de992557..520c0f54150 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -4056,6 +4056,31 @@ (define_insn "*large_load_address"
[(set_attr "type" "load")
(set (attr "length") (const_int 8))])
+;; The AND is redunant here. It always turns off the high 32 bits and the
+;; low number of bits equal to the shift count. Those upper 32 bits will be
+;; reset by the SIGN_EXTEND at the end.
+;;
+;; One could argue combine should have realized this and simplified what it
+;; presented to the backend. But we can obviously cope with what it gave us.
+(define_insn_and_split ""
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (sign_extend:DI
+ (plus:SI (subreg:SI
+ (and:DI
+ (ashift:DI (match_operand:DI 1 "register_operand" "r")
+ (match_operand 2 "const_int_operand" "n"))
+ (match_operand 3 "const_int_operand" "n")) 0)
+ (match_operand:SI 4 "register_operand" "r"))))
+ (clobber (match_scratch:DI 5 "=&r"))]
+ "TARGET_64BIT
+ && (INTVAL (operands[3]) | ((1 << INTVAL (operands[2])) - 1)) == 0xffffffff"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 5) (ashift:DI (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 6) (match_dup 4))))]
+ "{ operands[6] = gen_lowpart (SImode, operands[5]); }"
+ [(set_attr "type" "arith")])
+
(include "bitmanip.md")
(include "crypto.md")
(include "sync.md")
diff --git a/gcc/testsuite/gcc.target/riscv/shift-add-2.c
b/gcc/testsuite/gcc.target/riscv/shift-add-2.c
new file mode 100644
index 00000000000..87439858e59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/shift-add-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+int sub2(int a, long long b) {
+ b = (b << 32) >> 31;
+ unsigned int x = a + b;
+ return x;
+}
+
+
+/* { dg-final { scan-assembler-times "\tslli\t" 1 } } */
+/* { dg-final { scan-assembler-times "\taddw\t" 1 } } */
+/* { dg-final { scan-assembler-not "\tsrai\t" } } */
+/* { dg-final { scan-assembler-not "\tsh.add\t" } } */
+
