LGTM :)
On Wed, May 15, 2024 at 2:48 PM Christoph Müllner
<christoph.muell...@vrull.eu> wrote:
>
> Emitting a DI pattern won't find a match for rv32 and manifests in
> the failing test case gcc.target/riscv/cmo-zicboz-zic64-1.c.
> Let's fix this in the expansion and also address the different
> code that gets generated for rv32/rv64.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-string.cc
> (riscv_expand_block_clear_zicboz_zic64b):
> Fix expansion for rv32.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/cmo-zicboz-zic64-1.c: Fix for rv32.
>
> Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
> ---
> gcc/config/riscv/riscv-string.cc | 5 ++-
> .../gcc.target/riscv/cmo-zicboz-zic64-1.c | 36 ++++++-------------
> 2 files changed, 14 insertions(+), 27 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-string.cc
> b/gcc/config/riscv/riscv-string.cc
> index 87f5fdee3c1..b515f44d17a 100644
> --- a/gcc/config/riscv/riscv-string.cc
> +++ b/gcc/config/riscv/riscv-string.cc
> @@ -827,7 +827,10 @@ riscv_expand_block_clear_zicboz_zic64b (rtx dest, rtx
> length)
> {
> rtx mem = adjust_address (dest, BLKmode, offset);
> rtx addr = force_reg (Pmode, XEXP (mem, 0));
> - emit_insn (gen_riscv_zero_di (addr));
> + if (TARGET_64BIT)
> + emit_insn (gen_riscv_zero_di (addr));
> + else
> + emit_insn (gen_riscv_zero_si (addr));
> offset += cbo_bytes;
> }
>
> diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c
> b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c
> index c2d79eb7ae6..9192b391b11 100644
> --- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c
> @@ -1,25 +1,9 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zic64b_zicboz" { target { rv64 } } } */
> /* { dg-options "-march=rv32gc_zic64b_zicboz" { target { rv32 } } } */
> +/* { dg-options "-march=rv64gc_zic64b_zicboz" { target { rv64 } } } */
> /* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
> -/* { dg-final { check-function-bodies "**" "" } } */
> -/* { dg-allow-blank-lines-in-output 1 } */
>
> -/*
> -**clear_buf_123:
> -** ...
> -** cbo\.zero\t0\(a[0-9]+\)
> -** sd\tzero,64\(a[0-9]+\)
> -** sd\tzero,72\(a[0-9]+\)
> -** sd\tzero,80\(a[0-9]+\)
> -** sd\tzero,88\(a[0-9]+\)
> -** sd\tzero,96\(a[0-9]+\)
> -** sd\tzero,104\(a[0-9]+\)
> -** sd\tzero,112\(a[0-9]+\)
> -** sh\tzero,120\(a[0-9]+\)
> -** sb\tzero,122\(a[0-9]+\)
> -** ...
> -*/
> +// 1x cbo.zero, 7x sd (rv64) or 14x sw (rv32), 1x sh, 1x sb
> int
> clear_buf_123 (void *p)
> {
> @@ -27,17 +11,17 @@ clear_buf_123 (void *p)
> __builtin_memset (p, 0, 123);
> }
>
> -/*
> -**clear_buf_128:
> -** ...
> -** cbo\.zero\t0\(a[0-9]+\)
> -** addi\ta[0-9]+,a[0-9]+,64
> -** cbo\.zero\t0\(a[0-9]+\)
> -** ...
> -*/
> +// 2x cbo.zero, 1x addi 64
> int
> clear_buf_128 (void *p)
> {
> p = __builtin_assume_aligned(p, 64);
> __builtin_memset (p, 0, 128);
> }
> +
> +/* { dg-final { scan-assembler-times "cbo\.zero\t" 3 } } */
> +/* { dg-final { scan-assembler-times "addi\ta\[0-9\]+,a\[0-9\]+,64" 1 } } */
> +/* { dg-final { scan-assembler-times "sd\t" 7 { target { rv64 } } } } */
> +/* { dg-final { scan-assembler-times "sw\t" 14 { target { rv32 } } } } */
> +/* { dg-final { scan-assembler-times "sh\t" 1 } } */
> +/* { dg-final { scan-assembler-times "sb\t" 1 } } */
> --
> 2.44.0
>
