Committed with more comments, thanks Robin.
Pan
-----Original Message-----
From: Robin Dapp <rdapp....@gmail.com>
Sent: Saturday, May 18, 2024 3:32 AM
To: Li, Pan2 <pan2...@intel.com>; gcc-patches@gcc.gnu.org
Cc: rdapp....@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: Re: [PATCH v6] RISC-V: Implement IFN SAT_ADD for both the scalar and
vector
Hi Pan,
all in all LGTM. Just insignificant nits.
> +void
> +expand_vec_usadd (rtx op_0, rtx op_1, rtx op_2, machine_mode vec_mode)
> +{
> + emit_vec_saddu (op_0, op_1, op_2, BINARY_OP, vec_mode);
> +}
> +
Do we really need this function? Or do you want it to be a dispatcher
for later? If it should do more than just a call, please document.
> + /* Step-1: sum = x + y */
> + if (mode == SImode && mode != Xmode)
> + { /* Take addw to avoid the sum truncate. */
> + rtx simode_sum = gen_reg_rtx (SImode);
> + riscv_emit_binary (PLUS, simode_sum, x, y);
> + emit_move_insn (xmode_sum, gen_lowpart (Xmode, simode_sum));
> + }
> + else
> + riscv_emit_binary (PLUS, xmode_sum, xmode_x, xmode_y);
I would add a top-level comment that the emulation is just
sum = x + y;
if (sum < x)
sum = TYPE_MAX;
and we can implement the if/then by sltu and or.
No need for another revision, though.
Regards
Robin
