gcc/ChangeLog:
* config/i386/i386.md (ashr<mode>3_cvt_nf): New define_insn.
(*<insn><mode>3_1_nf): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-nf.c: Add NF test for rotate insns.
---
gcc/config/i386/i386.md | 53 ++++++++++++++++----------
gcc/testsuite/gcc.target/i386/apx-nf.c | 5 +++
2 files changed, 38 insertions(+), 20 deletions(-)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index
7f191749342..731eb12d13a 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -16230,19 +16230,19 @@
(define_mode_attr cvt_mnemonic
[(SI "{cltd|cdq}") (DI "{cqto|cqo}")])
-(define_insn "ashr<mode>3_cvt"
+(define_insn "ashr<mode>3_cvt<nf_name>"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=*d,rm,r")
(ashiftrt:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "*a,0,rm")
- (match_operand:QI 2 "const_int_operand")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "const_int_operand")))]
"INTVAL (operands[2]) == GET_MODE_BITSIZE (<MODE>mode)-1
&& (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
- && ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)"
+ && ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)
+ && <nf_condition>"
"@
<cvt_mnemonic>
- sar{<imodesuffix>}\t{%2, %0|%0, %2}
- sar{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ <nf_prefix>sar{<imodesuffix>}\t{%2, %0|%0, %2}
+ <nf_prefix>sar{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "*,*,apx_ndd")
(set_attr "type" "imovx,ishift,ishift")
(set_attr "prefix_0f" "0,*,*")
@@ -17094,13 +17094,13 @@
[(set_attr "type" "rotatex")
(set_attr "mode" "<MODE>")])
-(define_insn "*<insn><mode>3_1"
+(define_insn "*<insn><mode>3_1<nf_name>"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r")
(any_rotate:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "0,rm,rm")
- (match_operand:QI 2 "nonmemory_operand" "c<S>,<S>,c<S>")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands, TARGET_APX_NDD)"
+ (match_operand:QI 2 "nonmemory_operand" "c<S>,<S>,c<S>")))]
+ "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands, TARGET_APX_NDD)
+ && <nf_condition>"
{
bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
switch (get_attr_type (insn))
@@ -17111,11 +17111,11 @@
default:
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && !use_ndd)
+ && !use_ndd && !<nf_applied>)
return "<rotate>{<imodesuffix>}\t%0";
else
- return use_ndd ? "<rotate>{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
- : "<rotate>{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return use_ndd ? "<nf_prefix><rotate>{<imodesuffix>}\t{%2, %1, %0|%0,
%1, %2}"
+ : "<nf_prefix><rotate>{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set_attr "isa" "*,bmi2,apx_ndd")
@@ -17135,6 +17135,19 @@
(set_attr "mode" "<MODE>")])
;; Convert rotate to the rotatex pattern to avoid flags dependency.
+(define_split
+ [(set (match_operand:SWI48 0 "register_operand")
+ (rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+ (match_operand:QI 2 "const_int_operand")))]
+ "TARGET_BMI2 && reload_completed && !optimize_function_for_size_p (cfun)"
+ [(set (match_dup 0)
+ (rotatert:SWI48 (match_dup 1) (match_dup 2)))] {
+ int bitsize = GET_MODE_BITSIZE (<MODE>mode);
+
+ operands[2] = GEN_INT ((bitsize - INTVAL (operands[2])) % bitsize);
+})
+
(define_split
[(set (match_operand:SWI48 0 "register_operand")
(rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") @@
-17236,22 +17249,22 @@
[(set (match_dup 0)
(zero_extend:DI (rotatert:SI (match_dup 1) (match_dup 2))))])
-(define_insn "*<insn><mode>3_1"
+(define_insn "*<insn><mode>3_1<nf_name>"
[(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m,r")
(any_rotate:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "0,rm")
- (match_operand:QI 2 "nonmemory_operand" "c<S>,c<S>")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands, TARGET_APX_NDD)"
+ (match_operand:QI 2 "nonmemory_operand"
"c<S>,c<S>")))]
+ "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands, TARGET_APX_NDD)
+ && <nf_condition>"
{
bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && !use_ndd)
+ && !use_ndd && !<nf_applied>)
return "<rotate>{<imodesuffix>}\t%0";
else
return use_ndd
- ? "<rotate>{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
- : "<rotate>{<imodesuffix>}\t{%2, %0|%0, %2}";
+ ? "<nf_prefix><rotate>{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ : "<nf_prefix><rotate>{<imodesuffix>}\t{%2, %0|%0, %2}";
}
[(set_attr "isa" "*,apx_ndd")
(set_attr "type" "rotate")
diff --git a/gcc/testsuite/gcc.target/i386/apx-nf.c
b/gcc/testsuite/gcc.target/i386/apx-nf.c
index 608dbf8f5f7..6e59803be64 100644
--- a/gcc/testsuite/gcc.target/i386/apx-nf.c
+++ b/gcc/testsuite/gcc.target/i386/apx-nf.c
@@ -3,6 +3,7 @@
/* { dg-final { scan-assembler-times "\{nf\} add" 4 } } */
/* { dg-final { scan-assembler-times "\{nf\} and" 1 } } */
/* { dg-final { scan-assembler-times "\{nf\} or" 1 } } */
+/* { dg-final { scan-assembler-times "\{nf\} rol" 4 } } */
#include "apx-ndd.c"
@@ -13,3 +14,7 @@ foo (struct B *b)
{
b->bit0 = b->bit0 | b->bit1;
}
+long int f1 (int x) { return ~(1ULL << (x & 0x3f)); } long int f2 (int
+x) { return ~(1ULL << x); } long int f3 (unsigned char *x) { return
+~(1ULL << (x[0] & 0x3f)); } long int f4 (unsigned char *x) { return
+~(1ULL << x[0]); }
--
2.31.1
