On Fri, Jul 12, 2024 at 12:41:38PM +0800, MayShao-oc wrote: > From: mayshao <mayshao...@zhaoxin.com> > > Hi all: > We reply in PR104688 that ZHAOXIN guarantees that 16-byte VMOVDQA on > 16-byte aligned address is atomic, if memory type of the address is WB. So > there is no need to clear bit_AVX on ZHAOXIN CPUs. > > Bootstrapped /regtested X86_64. > > Ok for trunk? > BR > Mayshao > > libatomic/ChangeLog: > > PR target/104688 > * config/x86/init.c (__libat_feat1_init): Don't clear > bit_AVX on ZHAOXIN CPUs.
Does that above guarantee also extend to the VIA CPUs with AVX, I think that is Eden X4 C4450, Eden X4 C4250, Eden X1 C1050, Nano C QuadCore C4650 and maybe the CNS core? Because beyond Intel, AMD and Zhaoxin those VIAs are the remaining CPUs with AVX ISA support. If not, then we should just amend this to handle Zhaoxin too, if yes, we should also reconsider the https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606022.html patch. > diff --git a/libatomic/config/x86/init.c b/libatomic/config/x86/init.c > index a75be3f175c..3740c88a936 100644 > --- a/libatomic/config/x86/init.c > +++ b/libatomic/config/x86/init.c > @@ -34,20 +34,6 @@ __libat_feat1_init (void) > unsigned int eax, ebx, ecx, edx; > FEAT1_REGISTER = 0; > __get_cpuid (1, &eax, &ebx, &ecx, &edx); > -#ifdef __x86_64__ > - if ((FEAT1_REGISTER & (bit_AVX | bit_CMPXCHG16B)) > - == (bit_AVX | bit_CMPXCHG16B)) > - { > - /* Intel SDM guarantees that 16-byte VMOVDQA on 16-byte aligned address > - is atomic, and AMD is going to do something similar soon. > - We don't have a guarantee from vendors of other CPUs with AVX, > - like Zhaoxin and VIA. */ > - unsigned int ecx2 = 0; > - __get_cpuid (0, &eax, &ebx, &ecx2, &edx); > - if (ecx2 != signature_INTEL_ecx && ecx2 != signature_AMD_ecx) > - FEAT1_REGISTER &= ~bit_AVX; > - } > -#endif > /* See the load in load_feat1. */ > __atomic_store_n (&__libat_feat1, FEAT1_REGISTER, __ATOMIC_RELAXED); > return FEAT1_REGISTER; > -- > 2.27.0 Jakub
