Vineet Gupta <[email protected]> writes: > On 8/19/24 14:52, Richard Sandiford wrote: >>> 2. On RISC-V sched1 is counter intuitively assuming HARD_FP is live due to >>> the weird interaction of DF infra (which always marks HARD_FP with >>> artificial def) and ira_no_alloc_regs. >> In general, it isn't possible to predict at this stage whether the hard >> frame pointer will be needed, even for -fomit-frame-pointer. The final >> decision is made during LRA, which in the worst case has iterate through >> several elimination attempts. >> >> So whatever we do here will be wrong for some cases. In some ways, >> assuming that the hard frame pointer will be needed is the conservative >> option; if we instead assumed that it wasn't needed, we'd be more >> willing to move code around to make use of that (supposed) extra register. > > Right, but we can tweak sched1 heuristics some more :-) > What if just for model pressure calculations we ignore these artificial defs > and FP semantics from RA pov remain unchanged.
But my point was that: - the sched1 code doesn't know whether FP will be needed - assuming that the FP will be needed should lead to a higher pressure estimate - a higher pressure estimate should lead to more caution - in general, more caution leads to less spilling The original report was about too much spilling. Making sched1 assume that it has more free registers is, in general, likely to increase the amount of spilling rather than reduce it. > As a crude hack I tried below (which doesn't do any sanity check for bitmap > validity) > > diff --git a/gcc/haifa-sched.cc b/gcc/haifa-sched.cc > > - EXECUTE_IF_SET_IN_BITMAP (live, 0, j, bi) > + EXECUTE_IF_AND_COMPL_IN_BITMAP (live, &df->regular_block_artificial_uses, > 0, j, bi) If this helps the SPEC benchmark, then for the reasons we discussed eariler with Jeff, I think it's likely just a coincidence, rather than the right fix. Thanks, Richard
