On 06/27/2012 09:07 AM, Igor Zamyatin wrote:
> May I ask about the purpose of the following piece of change? Doesn't
> it affect non-sse cases either?
Err, no, it doesn't affect non-sse cases. All MODE_VECTOR_INT
cases will be implemented in the xmm registers (ignoring the
deprecated and largely ignored mmx case).
>
> @@ -32038,7 +32042,15 @@ ix86_rtx_costs (rtx x, int code, int
> outer_code_i, int opno, int *total,
> case ASHIFTRT:
> case LSHIFTRT:
> case ROTATERT:
> - if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
> + if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
> + {
> + /* ??? Should be SSE vector operation cost. */
> + /* At least for published AMD latencies, this really is the same
> + as the latency for a simple fpu operation like fabs. */
> + *total = cost->fabs;
> + return false;
> + }
> + if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
> {
> if (CONST_INT_P (XEXP (x, 1)))
> {
>
> It also seems that we reversed the condition for the code that is now
> under if (GET_MODE_SIZE (mode) < UNITS_PER_WORD). Why do we need this?
I'm not sure what you're suggesting. But we certainly don't use
the xmm registers to implement DImode operations in 32-bit, so...
r~
