On 04/09/2024 14:26, Christophe Lyon wrote: > Factorize vdwdup and viwdup so that they use the same parameterized > names. > > Like with vddup and vidup, we do not bother with the corresponding > expanders, as we stop using them in a subsequent patch. > > The patch also adds the missing attributes to vdwdupq_wb_u_insn and > viwdupq_wb_u_insn patterns. > > 2024-08-21 Christophe Lyon <christophe.l...@linaro.org> > > gcc/ > * config/arm/iterators.md (mve_insn): Add VIWDUPQ, VDWDUPQ, > VIWDUPQ_M, VDWDUPQ_M. > (VIDWDUPQ): New iterator. > (VIDWDUPQ_M): New iterator. > * config/arm/mve.md (mve_vdwdupq_wb_u<mode>_insn) > (mve_viwdupq_wb_u<mode>_insn): Merge into ... > (@mve_<mve_insn>q_wb_u<mode>_insn): ... this. Add missing > mve_unpredicated_insn and mve_move attributes. > (mve_vdwdupq_m_wb_u<mode>_insn, mve_viwdupq_m_wb_u<mode>_insn): > Merge into ... > (@mve_<mve_insn>q_m_wb_u<mode>_insn): ... this.
OK. R. > --- > gcc/config/arm/iterators.md | 4 +++ > gcc/config/arm/mve.md | 68 +++++++------------------------------ > 2 files changed, 17 insertions(+), 55 deletions(-) > > diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md > index c0299117f26..2fb3b25040f 100644 > --- a/gcc/config/arm/iterators.md > +++ b/gcc/config/arm/iterators.md > @@ -1009,6 +1009,8 @@ (define_int_attr mve_insn [ > (VHSUBQ_S "vhsub") (VHSUBQ_U "vhsub") > (VIDUPQ "vidup") (VDDUPQ "vddup") > (VIDUPQ_M "vidup") (VDDUPQ_M "vddup") > + (VIWDUPQ "viwdup") (VDWDUPQ "vdwdup") > + (VIWDUPQ_M "viwdup") (VDWDUPQ_M "vdwdup") > (VMAXAQ_M_S "vmaxa") > (VMAXAQ_S "vmaxa") > (VMAXAVQ_P_S "vmaxav") > @@ -2968,6 +2970,8 @@ (define_int_iterator VCVTxQ [VCVTAQ_S VCVTAQ_U VCVTMQ_S > VCVTMQ_U VCVTNQ_S VCVTNQ > (define_int_iterator VCVTxQ_M [VCVTAQ_M_S VCVTAQ_M_U VCVTMQ_M_S VCVTMQ_M_U > VCVTNQ_M_S VCVTNQ_M_U VCVTPQ_M_S VCVTPQ_M_U]) > (define_int_iterator VIDDUPQ [VIDUPQ VDDUPQ]) > (define_int_iterator VIDDUPQ_M [VIDUPQ_M VDDUPQ_M]) > +(define_int_iterator VIDWDUPQ [VIWDUPQ VDWDUPQ]) > +(define_int_iterator VIDWDUPQ_M [VIWDUPQ_M VDWDUPQ_M]) > (define_int_iterator DLSTP [DLSTP8 DLSTP16 DLSTP32 > DLSTP64]) > (define_int_iterator LETP [LETP8 LETP16 LETP32 > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index 3477bbdda7b..be3be67a144 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -5156,22 +5156,23 @@ (define_expand "mve_vdwdupq_wb_u<mode>" > }) > > ;; > -;; [vdwdupq_wb_u_insn]) > +;; [vdwdupq_wb_u_insn, viwdupq_wb_u_insn] > ;; > -(define_insn "mve_vdwdupq_wb_u<mode>_insn" > +(define_insn "@mve_<mve_insn>q_wb_u<mode>_insn" > [(set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") > (subreg:SI (match_operand:DI 3 "s_register_operand" "r") > 4) > (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")] > - VDWDUPQ)) > + VIDWDUPQ)) > (set (match_operand:SI 1 "s_register_operand" "=Te") > (unspec:SI [(match_dup 2) > (subreg:SI (match_dup 3) 4) > (match_dup 4)] > - VDWDUPQ))] > + VIDWDUPQ))] > "TARGET_HAVE_MVE" > - "vdwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4" > -) > + "<mve_insn>.u%#<V_sz_elem>\t%q0, %2, %R3, %4" > + [(set (attr "mve_unpredicated_insn") (symbol_ref > "CODE_FOR_mve_<mve_insn>q_wb_u<mode>_insn")) > + (set_attr "type" "mve_move")]) > > ;; > ;; [vdwdupq_m_n_u]) > @@ -5214,27 +5215,27 @@ (define_expand "mve_vdwdupq_m_wb_u<mode>" > }) > > ;; > -;; [vdwdupq_m_wb_u_insn]) > +;; [vdwdupq_m_wb_u_insn, viwdupq_m_wb_u_insn] > ;; > -(define_insn "mve_vdwdupq_m_wb_u<mode>_insn" > +(define_insn "@mve_<mve_insn>q_m_wb_u<mode>_insn" > [(set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") > (match_operand:SI 3 "s_register_operand" "1") > (subreg:SI (match_operand:DI 4 "s_register_operand" "r") > 4) > (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg") > (match_operand:<MVE_VPRED> 6 "vpr_register_operand" > "Up")] > - VDWDUPQ_M)) > + VIDWDUPQ_M)) > (set (match_operand:SI 1 "s_register_operand" "=Te") > (unspec:SI [(match_dup 2) > (match_dup 3) > (subreg:SI (match_dup 4) 4) > (match_dup 5) > (match_dup 6)] > - VDWDUPQ_M)) > + VIDWDUPQ_M)) > ] > "TARGET_HAVE_MVE" > - "vpst\;vdwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5" > - [(set (attr "mve_unpredicated_insn") (symbol_ref > "CODE_FOR_mve_vdwdupq_wb_u<mode>_insn")) > + "vpst\;<mve_insn>t.u%#<V_sz_elem>\t%q2, %3, %R4, %5" > + [(set (attr "mve_unpredicated_insn") (symbol_ref > "CODE_FOR_mve_<mve_insn>q_wb_u<mode>_insn")) > (set_attr "type" "mve_move") > (set_attr "length""8")]) > > @@ -5273,24 +5274,6 @@ (define_expand "mve_viwdupq_wb_u<mode>" > DONE; > }) > > -;; > -;; [viwdupq_wb_u_insn]) > -;; > -(define_insn "mve_viwdupq_wb_u<mode>_insn" > - [(set (match_operand:MVE_2 0 "s_register_operand" "=w") > - (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") > - (subreg:SI (match_operand:DI 3 "s_register_operand" "r") > 4) > - (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")] > - VIWDUPQ)) > - (set (match_operand:SI 1 "s_register_operand" "=Te") > - (unspec:SI [(match_dup 2) > - (subreg:SI (match_dup 3) 4) > - (match_dup 4)] > - VIWDUPQ))] > - "TARGET_HAVE_MVE" > - "viwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4" > -) > - > ;; > ;; [viwdupq_m_n_u]) > ;; > @@ -5331,31 +5314,6 @@ (define_expand "mve_viwdupq_m_wb_u<mode>" > DONE; > }) > > -;; > -;; [viwdupq_m_wb_u_insn]) > -;; > -(define_insn "mve_viwdupq_m_wb_u<mode>_insn" > - [(set (match_operand:MVE_2 0 "s_register_operand" "=w") > - (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") > - (match_operand:SI 3 "s_register_operand" "1") > - (subreg:SI (match_operand:DI 4 "s_register_operand" "r") > 4) > - (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg") > - (match_operand:<MVE_VPRED> 6 "vpr_register_operand" > "Up")] > - VIWDUPQ_M)) > - (set (match_operand:SI 1 "s_register_operand" "=Te") > - (unspec:SI [(match_dup 2) > - (match_dup 3) > - (subreg:SI (match_dup 4) 4) > - (match_dup 5) > - (match_dup 6)] > - VIWDUPQ_M)) > - ] > - "TARGET_HAVE_MVE" > - "vpst\;\tviwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5" > - [(set (attr "mve_unpredicated_insn") (symbol_ref > "CODE_FOR_mve_viwdupq_wb_u<mode>_insn")) > - (set_attr "type" "mve_move") > - (set_attr "length""8")]) > - > ;; > ;; [vstrwq_scatter_base_wb_s vstrwq_scatter_base_wb_u] > ;;
