This patch tests if simd uniform clause works with SVE types in simd regions.
libgomp/ChangeLog:
* testsuite/libgomp.target/aarch64/simd-uniform.c: New.
---
.../libgomp.target/aarch64/simd-uniform.c | 83 +++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 libgomp/testsuite/libgomp.target/aarch64/simd-uniform.c
diff --git a/libgomp/testsuite/libgomp.target/aarch64/simd-uniform.c
b/libgomp/testsuite/libgomp.target/aarch64/simd-uniform.c
new file mode 100644
index 00000000000..48a8a91b004
--- /dev/null
+++ b/libgomp/testsuite/libgomp.target/aarch64/simd-uniform.c
@@ -0,0 +1,83 @@
+/* { dg-do run { target aarch64_sve256_hw } } */
+/* { dg-options "-msve-vector-bits=256 -std=gnu99 -fopenmp -O2" } */
+
+#include <arm_sve.h>
+
+#define N 256
+
+void
+init (int *a, int *a_ref, int *b, int n)
+{
+ int i;
+ for (i = 0; i < N; i++)
+ {
+ a[i] = i;
+ a_ref[i] = i;
+ b[i] = N-i;
+ }
+}
+
+void vec_add (svint32_t ones, int *a, int *b, int i, int64_t sz);
+
+#pragma omp declare simd uniform(ones, a, b, sz) linear (i)
+void
+vec_add (svint32_t ones, int *a, int *b, int i, int64_t sz)
+{
+ svint32_t tmp;
+ svint32_t va, vb;
+
+ va = svld1_s32 (svptrue_b32 (), a + i * sz);
+ vb = svld1_s32 (svptrue_b32 (), b + i * sz);
+ tmp = svadd_s32_z (svptrue_b32 (), va, vb);
+ tmp = svadd_s32_z (svptrue_b32 (), tmp, ones);
+ svst1_s32 (svptrue_b32 (), a + i * sz, tmp);
+}
+
+void
+work (int *a, int *b, int n)
+{
+ int i;
+ int64_t sz = svcntw ();
+
+ #pragma omp simd
+ for (i = 0; i < n/sz; i++)
+ {
+ svint32_t va, vb;
+ svint32_t ones = svdup_n_s32 (1);
+ vec_add (ones, a, b, i, sz);
+ }
+}
+
+void
+work_ref (int *a, int *b, int n)
+{
+ int i;
+ for ( i = 0; i < n; i++ ) {
+ a[i] = a[i] + b[i] + 1;
+ }
+}
+
+void
+check (int *a, int *b)
+{
+ int i;
+ for (i = 0; i < N; i++)
+ if (a[i] != b[i])
+ __builtin_abort ();
+}
+
+int
+main ()
+{
+ int i;
+ int a[N], a_ref[N], b[N];
+
+ init(a, a_ref, b, N);
+
+ work(a, b, N );
+ work_ref(a_ref, b, N );
+
+ check(a, a_ref);
+
+ return 0;
+}
--
2.25.1
