Re: [PATCH] testsuite: arm: Relax expected asm in bitfield* and union-2 tests

[Richard Earnshaw (lists)]

On 20/10/2024 16:49, Torbjörn SVENSSON wrote:

Ok for trunk and releases/gcc-14?

--

Below -O2, lsls/lsrs are prefered. For -O2 and above, lsl/lsr are
prefered.

gcc/testsuite/ChangeLog:

        * gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: Allow lsl and
        lsr instructions.
        * gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: Likewise.
        * gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c: Likewise.
        * gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c: Likewise.
        * gcc.target/arm/cmse/mainline/8_1m/union-2.c: Likewise.

OK

R.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svens...@foss.st.com>
---
  gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c  | 4 ++--
  gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c  | 4 ++--
  gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c  | 4 ++--
  .../gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c    | 4 ++--
  gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-2.c     | 4 ++--
  5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c 
b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c
index ff34edb21c3..4bdc09c0eab 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c
@@ -11,8 +11,8 @@
  /* { dg-final { scan-assembler "mov\tip, #3" } } */
  /* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
  /* Shift on the same register as blxns.  */
-/* { dg-final { scan-assembler "lsrs\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
-/* { dg-final { scan-assembler "lsls\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
+/* { dg-final { scan-assembler "lsrs?\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
+/* { dg-final { scan-assembler "lsls?\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
  /* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } 
} */
  /* Check the right registers are cleared and none appears twice.  */
  /* { dg-final { scan-assembler "clrm\t\{(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, 
)?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c 
b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c
index 9b1227adfdc..717b0e886c8 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c
@@ -12,8 +12,8 @@
  /* { dg-final { scan-assembler "mov\tip, #255" } } */
  /* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
  /* Shift on the same register as blxns.  */
-/* { dg-final { scan-assembler "lsrs\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
-/* { dg-final { scan-assembler "lsls\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
+/* { dg-final { scan-assembler "lsrs?\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
+/* { dg-final { scan-assembler "lsls?\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
  /* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } 
} */
  /* Check the right registers are cleared and none appears twice.  */
  /* { dg-final { scan-assembler "clrm\t\{(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, 
)?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c 
b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c
index ae039e292d5..03abd3e9542 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c
@@ -12,8 +12,8 @@
  /* { dg-final { scan-assembler "movt\tip, 31" } } */
  /* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
  /* Shift on the same register as blxns.  */
-/* { dg-final { scan-assembler "lsrs\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
-/* { dg-final { scan-assembler "lsls\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
+/* { dg-final { scan-assembler "lsrs?\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
+/* { dg-final { scan-assembler "lsls?\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
  /* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } 
} */
  /* Check the right registers are cleared and none appears twice.  */
  /* { dg-final { scan-assembler "clrm\t\{(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, 
)?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */
diff --git 
a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c 
b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c
index 3e76364c404..635189d77e5 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c
@@ -16,8 +16,8 @@
  /* { dg-final { scan-assembler "movt\tip, 31" } } */
  /* { dg-final { scan-assembler "and\tr3, r3, ip" } } */
  /* Shift on the same register as blxns.  */
-/* { dg-final { scan-assembler "lsrs\t(r\[4-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
-/* { dg-final { scan-assembler "lsls\t(r\[4-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
+/* { dg-final { scan-assembler "lsrs?\t(r\[4-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
+/* { dg-final { scan-assembler "lsls?\t(r\[4-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
  /* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } 
} */
  /* Check the right registers are cleared and none appears twice.  */
  /* { dg-final { scan-assembler "clrm\t\{(r4, )?(r5, )?(r6, )?(r7, )?(r8, )?(r9, 
)?(r10, )?(fp, )?(ip, )?APSR\}" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-2.c 
b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-2.c
index 95de458b501..90948610122 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-2.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-2.c
@@ -13,8 +13,8 @@
  /* { dg-final { scan-assembler "movt\tip, 31" } } */
  /* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
  /* Shift on the same register as blxns.  */
-/* { dg-final { scan-assembler "lsrs\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
-/* { dg-final { scan-assembler "lsls\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
+/* { dg-final { scan-assembler "lsrs?\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
+/* { dg-final { scan-assembler "lsls?\t(r\[3-9\]|r10|fp|ip), \\1, 
#1.*blxns\t\\1" } } */
  /* { dg-final { scan-assembler "push\t\{r4, r5, r6, r7, r8, r9, r10, fp\}" } 
} */
  /* Check the right registers are cleared and none appears twice.  */
  /* { dg-final { scan-assembler "clrm\t\{(r3, )?(r4, )?(r5, )?(r6, )?(r7, )?(r8, 
)?(r9, )?(r10, )?(fp, )?(ip, )?APSR\}" } } */