diff --git a/gcc/common/config/aarch64/aarch64-common.cc b/gcc/common/config/aarch64/aarch64-common.cc
index 2bfc597e333b6018970a9ee6e370a66b6d0960ef..2134a890eb7a0aaa62b58843f149c4a0db16bb89 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -447,6 +447,33 @@ aarch64_rewrite_mcpu (int argc, const char **argv)
   return aarch64_rewrite_selected_cpu (argv[argc - 1]);
 }
 
+/* Checks to see if the host CPU may not be Cortex-A53 or an unknown Armv8-a
+   baseline CPU.  */
+
+const char *
+is_host_cpu_not_armv8_base (int argc, const char **argv)
+{
+  gcc_assert (argc);
+
+  /* Default to not knowing what we are if unspecified.  The SPEC file should
+     have already mapped configure time options to here through
+     OPTION_DEFAULT_SPECS so we don't need to check the configure variants
+     manually.  */
+  if (!argv[0])
+    return NULL;
+
+  const char *res = argv[0];
+
+  /* No SVE system is baseline Armv8-A.  */
+  if (strstr (res, "+sve"))
+    return "";
+
+  if (strstr (res, "cortex-a53") || strstr (res, "armv8-a"))
+    return NULL;
+
+  return "";
+}
+
 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
 
 #undef AARCH64_CPU_NAME_LENGTH
diff --git a/gcc/config/aarch64/aarch64-elf-raw.h b/gcc/config/aarch64/aarch64-elf-raw.h
index 5396da9b2d626e23e4c4d56e19cd7aa70804c475..8442a664c4fdedd9696da90e6727293c4d472a3f 100644
--- a/gcc/config/aarch64/aarch64-elf-raw.h
+++ b/gcc/config/aarch64/aarch64-elf-raw.h
@@ -38,4 +38,12 @@
   AARCH64_ERRATA_LINK_SPEC
 #endif
 
+#ifndef CC1_SPEC
+# define CC1_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
+
+#ifndef CC1PLUS_SPEC
+# define CC1PLUS_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
+
 #endif /* GCC_AARCH64_ELF_RAW_H */
diff --git a/gcc/config/aarch64/aarch64-errata.h b/gcc/config/aarch64/aarch64-errata.h
index c323595ee49553f2b3bc106e993c14f62aee235b..dfc94488901c5a77c6c9f9a74166525c8a0e6668 100644
--- a/gcc/config/aarch64/aarch64-errata.h
+++ b/gcc/config/aarch64/aarch64-errata.h
@@ -21,24 +21,61 @@
 #ifndef GCC_AARCH64_ERRATA_H
 #define GCC_AARCH64_ERRATA_H
 
+/* Completely ignore the option if we've explicitly specify something other than
+   mcpu=cortex-a53 or march=armv8-a.  */
+#define TARGET_SUPPRESS_OPT_SPEC(OPT) \
+    "mcpu=*:%{%:is_local_not_armv8_base(%{mcpu=*:%*}):; " OPT \
+    "}; march=*:%{%:is_local_not_armv8_base(%{march=*:%*}):;" OPT "}; " OPT
+
+/* Explicitly turn off the option if we've explicitly specify something other
+   than mcpu=cortex-a53 or march=armv8-a.  This will also erase any other usage
+   of the flag making the order of the options not relevant.  */
+# define TARGET_TURN_OFF_OPT_SPEC(FLAG)  \
+   "mcpu=*:%{%:is_local_not_armv8_base(%{mcpu=*:%*}):%<m" FLAG " -mno-" FLAG \
+   "}; march=*:%{%:is_local_not_armv8_base(%{march=*:%*}):%<m" FLAG " -mno-" FLAG "}"
+
+/* Cortex-A53 835769 Errata.  */
+
 #if TARGET_FIX_ERR_A53_835769_DEFAULT
-#define CA53_ERR_835769_SPEC \
-  " %{!mno-fix-cortex-a53-835769:--fix-cortex-a53-835769}"
+#define CA53_ERR_835769_SPEC     \
+  " %{" \
+  TARGET_SUPPRESS_OPT_SPEC ("!mno-fix-cortex-a53-835769:--fix-cortex-a53-835769") \
+  " }"
 #else
-#define CA53_ERR_835769_SPEC \
-  " %{mfix-cortex-a53-835769:--fix-cortex-a53-835769}"
+#define CA53_ERR_835769_SPEC     \
+  " %{" \
+  TARGET_SUPPRESS_OPT_SPEC ("mfix-cortex-a53-835769:--fix-cortex-a53-835769") \
+  " }"
 #endif
 
+#define CA53_ERR_835769_COMPILE_SPEC \
+  " %{" TARGET_TURN_OFF_OPT_SPEC ("fix-cortex-a53-835769") "}"
+
+/* Cortex-A53 843419 Errata.  */
+
 #if TARGET_FIX_ERR_A53_843419_DEFAULT
-#define CA53_ERR_843419_SPEC \
-  " %{!mno-fix-cortex-a53-843419:--fix-cortex-a53-843419}"
+#define CA53_ERR_843419_SPEC     \
+  " %{" \
+  TARGET_SUPPRESS_OPT_SPEC ("!mno-fix-cortex-a53-843419:--fix-cortex-a53-843419") \
+  " }"
 #else
-#define CA53_ERR_843419_SPEC \
-  " %{mfix-cortex-a53-843419:--fix-cortex-a53-843419}"
+#define CA53_ERR_843419_SPEC     \
+  " %{" \
+  TARGET_SUPPRESS_OPT_SPEC ("mfix-cortex-a53-843419:--fix-cortex-a53-843419") \
+  " }"
 #endif
 
+#define CA53_ERR_843419_COMPILE_SPEC \
+  " %{" TARGET_TURN_OFF_OPT_SPEC ("fix-cortex-a53-843419") "}"
+
+/* Exports to use in SPEC files.  */
+
 #define AARCH64_ERRATA_LINK_SPEC		\
   CA53_ERR_835769_SPEC				\
   CA53_ERR_843419_SPEC
 
+#define AARCH64_ERRATA_COMPILE_SPEC		\
+  CA53_ERR_835769_COMPILE_SPEC			\
+  CA53_ERR_843419_COMPILE_SPEC
+
 #endif /*  GCC_AARCH64_ERRATA_H */
diff --git a/gcc/config/aarch64/aarch64-freebsd.h b/gcc/config/aarch64/aarch64-freebsd.h
index e26d69ce46c7376402c96b846e21a6c0846ebe04..8a76017538a121b4f8ce16d7a64a080d84c72e25 100644
--- a/gcc/config/aarch64/aarch64-freebsd.h
+++ b/gcc/config/aarch64/aarch64-freebsd.h
@@ -47,6 +47,14 @@
     -X" SUBTARGET_EXTRA_LINK_SPEC "                             \
     %{mbig-endian:-EB} %{mlittle-endian:-EL}"
 
+#ifndef CC1_SPEC
+# define CC1_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
+
+#ifndef CC1PLUS_SPEC
+# define CC1PLUS_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
+
 #undef  LINK_SPEC
 #define LINK_SPEC FBSD_TARGET_LINK_SPEC AARCH64_ERRATA_LINK_SPEC
 
diff --git a/gcc/config/aarch64/aarch64-gnu.h b/gcc/config/aarch64/aarch64-gnu.h
index ee54940342d3000513aef28d8b29a44d1424c41b..74456263e5837ea8a53b15ebf632ef5407ae2ffb 100644
--- a/gcc/config/aarch64/aarch64-gnu.h
+++ b/gcc/config/aarch64/aarch64-gnu.h
@@ -36,6 +36,13 @@
    %{mbig-endian:-EB} %{mlittle-endian:-EL}     \
    -maarch64gnu%{mabi=ilp32:32}%{mbig-endian:b}"
 
+#ifndef CC1_SPEC
+# define CC1_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
+
+#ifndef CC1PLUS_SPEC
+# define CC1PLUS_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
 
 #define LINK_SPEC GNU_TARGET_LINK_SPEC AARCH64_ERRATA_LINK_SPEC
 
diff --git a/gcc/config/aarch64/aarch64-linux.h b/gcc/config/aarch64/aarch64-linux.h
index 8e51c8202ccc87c19deb97e046ad688899680b62..7582d1734892dbbd550077b0f5a87e095f938ad8 100644
--- a/gcc/config/aarch64/aarch64-linux.h
+++ b/gcc/config/aarch64/aarch64-linux.h
@@ -29,8 +29,12 @@
 #undef  ASAN_CC1_SPEC
 #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
 
-#undef  CC1_SPEC
-#define CC1_SPEC GNU_USER_TARGET_CC1_SPEC ASAN_CC1_SPEC
+#undef CC1_SPEC
+#define CC1_SPEC GNU_USER_TARGET_CC1_SPEC ASAN_CC1_SPEC \
+    AARCH64_ERRATA_COMPILE_SPEC
+
+#undef CC1PLUS_SPEC
+#define CC1PLUS_SPEC AARCH64_ERRATA_COMPILE_SPEC
 
 #define CPP_SPEC "%{pthread:-D_REENTRANT}"
 
diff --git a/gcc/config/aarch64/aarch64-netbsd.h b/gcc/config/aarch64/aarch64-netbsd.h
index fb8d10ffd18f9152740199ad8c481fe2f13f3470..57fffcd448fd976b919cf874f00d3341dd6f0757 100644
--- a/gcc/config/aarch64/aarch64-netbsd.h
+++ b/gcc/config/aarch64/aarch64-netbsd.h
@@ -39,6 +39,15 @@
   "%{mlittle-endian:-EL -m " TARGET_LINKER_LITTLE_EMULATION "} "	\
   "%(netbsd_link_spec)"
 
+
+#ifndef CC1_SPEC
+# define CC1_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
+
+#ifndef CC1PLUS_SPEC
+# define CC1PLUS_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
+
 #undef  LINK_SPEC
 #define LINK_SPEC NETBSD_LINK_SPEC_ELF		\
 		  NETBSD_TARGET_LINK_SPEC	\
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index f463f1061e95a6ec818f4c982d883c2347afac88..2597c72656f447900ae916a61fccb7a2b1c0194a 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -1472,8 +1472,11 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
    " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}"
 
 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv);
-#define MCPU_TO_MARCH_SPEC_FUNCTIONS \
-  { "rewrite_mcpu", aarch64_rewrite_mcpu },
+extern const char *is_host_cpu_not_armv8_base (int argc, const char **argv);
+#define MCPU_TO_MARCH_SPEC_FUNCTIONS		       \
+  { "rewrite_mcpu",            aarch64_rewrite_mcpu }, \
+  { "is_local_not_armv8_base", is_host_cpu_not_armv8_base },
+
 
 #define ASM_CPU_SPEC \
    MCPU_TO_MARCH_SPEC
diff --git a/gcc/config/aarch64/driver-aarch64.cc b/gcc/config/aarch64/driver-aarch64.cc
index abe6e7df7dc69cb8c435e5348463b93fa56986d1..03975258cf7ff29f06f9df8a7f3641ca5affc84b 100644
--- a/gcc/config/aarch64/driver-aarch64.cc
+++ b/gcc/config/aarch64/driver-aarch64.cc
@@ -480,4 +480,3 @@ not_found:
     return NULL;
   }
 }
-
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 0d66d2f83c42c292f25b765a7f187a9efc3d3810..9572436bceec6882f2637ec721499f3789c59cce 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21419,7 +21419,9 @@ This option requires binutils 2.26 or newer.
 @itemx -mno-fix-cortex-a53-835769
 Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769.
 This involves inserting a NOP instruction between memory instructions and
-64-bit integer multiply-accumulate instructions.
+64-bit integer multiply-accumulate instructions.  This flag will be ignored if
+an architecture or cpu is specified on the commandline which does not need the
+workaround.
 
 @opindex mfix-cortex-a53-843419
 @opindex mno-fix-cortex-a53-843419
@@ -21427,7 +21429,10 @@ This involves inserting a NOP instruction between memory instructions and
 @itemx -mno-fix-cortex-a53-843419
 Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419.
 This erratum workaround is made at link time and this will only pass the
-corresponding flag to the linker.
+corresponding flag to the linker.  This flag will be ignored if
+an architecture or cpu is specified on the commandline which does not need the
+workaround.
+
 
 @opindex mlow-precision-recip-sqrt
 @opindex mno-low-precision-recip-sqrt
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_30 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_30
new file mode 100644
index 0000000000000000000000000000000000000000..784ae11ef31d534dd31f97650ef60c9ad589037b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_30
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd03
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_31 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_31
new file mode 100644
index 0000000000000000000000000000000000000000..7fa7fac8c7a97564b4f71ec483e8a36d41e7c327
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_31
@@ -0,0 +1,9 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti paca pacg
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xfff
+CPU revision	: 2
+
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_32 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_32
new file mode 100644
index 0000000000000000000000000000000000000000..784ae11ef31d534dd31f97650ef60c9ad589037b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_32
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd03
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_33 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_33
new file mode 100644
index 0000000000000000000000000000000000000000..7fa7fac8c7a97564b4f71ec483e8a36d41e7c327
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_33
@@ -0,0 +1,9 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti paca pacg
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xfff
+CPU revision	: 2
+
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_30.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_30.c
new file mode 100644
index 0000000000000000000000000000000000000000..d35323e1a85d1c369f0e097d192de0054abd7f6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_30.c
@@ -0,0 +1,14 @@
+/* { dg-do link { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_30" } */
+/* { dg-additional-options "-mcpu=native -mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
+
+/* Test a normal looking procinfo.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_31.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_31.c
new file mode 100644
index 0000000000000000000000000000000000000000..fe74126d2a63fc1a32b6bad780d7bbd1b74c466a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_31.c
@@ -0,0 +1,14 @@
+/* { dg-do link { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_31" } */
+/* { dg-additional-options "-mcpu=native -mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
+
+/* Check that an Armv8-A core doesn't fall apart on extensions without midr
+   values and that it enables optional features.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_32.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_32.c
new file mode 100644
index 0000000000000000000000000000000000000000..3e4a6ee17855154e13703c98b978acbd2f050bcb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_32.c
@@ -0,0 +1,14 @@
+/* { dg-do link { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_32" } */
+/* { dg-additional-options "-mcpu=native -mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
+
+/* Test a normal looking procinfo.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_33.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_33.c
new file mode 100644
index 0000000000000000000000000000000000000000..dacc1bda5f0cf18c61a0d3a6001637c871ae2242
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_33.c
@@ -0,0 +1,14 @@
+/* { dg-do link { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_33" } */
+/* { dg-additional-options "-mcpu=native -mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
+
+/* Check that an Armv8-A core doesn't fall apart on extensions without midr
+   values and that it enables optional features.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_0.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_0.c
new file mode 100644
index 0000000000000000000000000000000000000000..14ad5823a45dbc1e66a9919f3f58b290e974a13e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_0.c
@@ -0,0 +1,10 @@
+/* { dg-do link } */
+/* { dg-additional-options "-mcpu=neoverse-v1 -mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_1.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..6d4af751accc5a1fa485993a1711cc6c9afba3ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_1.c
@@ -0,0 +1,11 @@
+/* { dg-do link } */
+/* { dg-additional-options "-mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_10.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_10.c
new file mode 100644
index 0000000000000000000000000000000000000000..751493ec12603cbc1ea33e8bcd67540fbe78cc06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_10.c
@@ -0,0 +1,10 @@
+/* { dg-do link } */
+/* { dg-additional-options "-mfix-cortex-a53-843419 -mcpu=neoverse-v1 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_11.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_11.c
new file mode 100644
index 0000000000000000000000000000000000000000..430dbf48c02be033dfbb9e8fae7229da6aa0af89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_11.c
@@ -0,0 +1,10 @@
+/* { dg-do link } */
+/* { dg-additional-options "-march=armv9-a -mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_12.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_12.c
new file mode 100644
index 0000000000000000000000000000000000000000..8ffd54f3897337b2d9fc22595adc0e4c06bc3d8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_12.c
@@ -0,0 +1,10 @@
+/* { dg-do link } */
+/* { dg-additional-options "-mfix-cortex-a53-843419 -march=armv9-a -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_13.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_13.c
new file mode 100644
index 0000000000000000000000000000000000000000..e027787c1ccdbb7297bf221f7d15fe22fb7c669a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_13.c
@@ -0,0 +1,11 @@
+/* { dg-do link } */
+/* { dg-additional-options "-mcpu=cortex-a53 -mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_14.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_14.c
new file mode 100644
index 0000000000000000000000000000000000000000..0c44aecc77f21ff34b0f2408c9b448efbc24cabd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_14.c
@@ -0,0 +1,11 @@
+/* { dg-do link } */
+/* { dg-additional-options "-march=armv8-a -mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_15.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_15.c
new file mode 100644
index 0000000000000000000000000000000000000000..015c507a655d8c5a5386b6da8218b1f62b2c4f31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_15.c
@@ -0,0 +1,11 @@
+/* { dg-do link } */
+/* { dg-additional-options "-mcpu=neoverse-v1 -march=armv8-a -mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* The input is conflicting, but take cpu over arch.  */
+/* { dg-message "-mno-fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_2.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..4f222863db66c3bd5d5b6cbee3633f5bd283da4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_2.c
@@ -0,0 +1,10 @@
+/* { dg-do link } */
+/* { dg-additional-options "-mfix-cortex-a53-835769 -mcpu=neoverse-v1 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_3.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..6d5ce4266706947f21e185395a174db5d64d8232
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_3.c
@@ -0,0 +1,10 @@
+/* { dg-do link } */
+/* { dg-additional-options "-march=armv9-a -mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_4.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_4.c
new file mode 100644
index 0000000000000000000000000000000000000000..29f994ce696f76421214fe7b87b83cfbc7c68697
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_4.c
@@ -0,0 +1,10 @@
+/* { dg-do link } */
+/* { dg-additional-options "-mfix-cortex-a53-835769 -march=armv9-a -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_5.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_5.c
new file mode 100644
index 0000000000000000000000000000000000000000..04b17062cefa97098c735928f09004fb46288131
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_5.c
@@ -0,0 +1,11 @@
+/* { dg-do link } */
+/* { dg-additional-options "-mcpu=cortex-a53 -mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_6.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_6.c
new file mode 100644
index 0000000000000000000000000000000000000000..2c71c27f9571f34ee6976558940272234269a62d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_6.c
@@ -0,0 +1,11 @@
+/* { dg-do link } */
+/* { dg-additional-options "-march=armv8-a -mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_7.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_7.c
new file mode 100644
index 0000000000000000000000000000000000000000..bea4629af1e74f2977e5e81a3a812ee09bf8f9df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_7.c
@@ -0,0 +1,11 @@
+/* { dg-do link } */
+/* { dg-additional-options "-mcpu=neoverse-v1 -march=armv8-a -mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* The input is conflicting, but take cpu over arch.  */
+/* { dg-message "-mno-fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_8.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_8.c
new file mode 100644
index 0000000000000000000000000000000000000000..27c2da0c44aeeb99998790be5084db7c7b6fcde3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_8.c
@@ -0,0 +1,10 @@
+/* { dg-do link } */
+/* { dg-additional-options "-mcpu=neoverse-v1 -mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
diff --git a/gcc/testsuite/gcc.target/aarch64/erratas_opt_9.c b/gcc/testsuite/gcc.target/aarch64/erratas_opt_9.c
new file mode 100644
index 0000000000000000000000000000000000000000..e930e59e3a07677573354427e14614868ee928a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/erratas_opt_9.c
@@ -0,0 +1,11 @@
+/* { dg-do link } */
+/* { dg-additional-options "-mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */