This patch support svvptc extension[1]. To enable GCC to recognize and process svvptc extension correctly at compile time.
[1] https://github.com/riscv/riscv-svvptc gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New extension. * common/config/riscv/riscv-ext-bitmask.def (RISCV_EXT_BITMASK): Ditto. * config/riscv/riscv.opt: New mask. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-44.c: New test. add svvptc testsuite --- gcc/common/config/riscv/riscv-common.cc | 4 ++++ gcc/common/config/riscv/riscv-ext-bitmask.def | 2 ++ gcc/config/riscv/riscv.opt | 5 +++++ gcc/testsuite/gcc.target/riscv/arch-44.c | 5 +++++ 4 files changed, 16 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-44.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index b0e49eb82c0..4b57b57f6e4 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -405,6 +405,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"svinval", ISA_SPEC_CLASS_NONE, 1, 0}, {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0}, {"svpbmt", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svvptc", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1721,6 +1722,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL), RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT), + + RISCV_EXT_FLAG_ENTRY ("svvptc", x_riscv_ptc_subext, MASK_SVVPTC), + RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO), RISCV_EXT_FLAG_ENTRY ("xcvmac", x_riscv_xcv_subext, MASK_XCVMAC), diff --git a/gcc/common/config/riscv/riscv-ext-bitmask.def b/gcc/common/config/riscv/riscv-ext-bitmask.def index ca5df1740f3..c42ce152ce3 100644 --- a/gcc/common/config/riscv/riscv-ext-bitmask.def +++ b/gcc/common/config/riscv/riscv-ext-bitmask.def @@ -79,5 +79,7 @@ RISCV_EXT_BITMASK ("zcd", 1, 4) RISCV_EXT_BITMASK ("zcf", 1, 5) RISCV_EXT_BITMASK ("zcmop", 1, 6) RISCV_EXT_BITMASK ("zawrs", 1, 7) +RISCV_EXT_BITMASK ("svvptc", 1, 8) + #undef RISCV_EXT_BITMASK diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index ab9d6e82723..3d9aae80858 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -466,6 +466,11 @@ Mask(SVINVAL) Var(riscv_sv_subext) Mask(SVNAPOT) Var(riscv_sv_subext) +TargetVariable +int riscv_ptc_subext + +Mask(SVVPTC) Var(riscv_ptc_subext) + TargetVariable int riscv_ztso_subext diff --git a/gcc/testsuite/gcc.target/riscv/arch-44.c b/gcc/testsuite/gcc.target/riscv/arch-44.c new file mode 100644 index 00000000000..80dc19a7083 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-44.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_svvptc -mabi=lp64" } */ +int foo() +{ +} -- 2.43.0
