This patch support ssdbltrp[1] and smdbltrp[2] extension. To enable GCC to recognize and process ssdbltrp and smdbltrp extension correctly at compile time.
[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc [2] https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New extension. * common/config/riscv/riscv-ext-bitmask.def (RISCV_EXT_BITMASK): Ditto. * config/riscv/riscv.opt: New mask. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-45.c: New test. * gcc.target/riscv/arch-46.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 6 ++++++ gcc/common/config/riscv/riscv-ext-bitmask.def | 2 ++ gcc/config/riscv/riscv.opt | 2 ++ gcc/testsuite/gcc.target/riscv/arch-45.c | 5 +++++ gcc/testsuite/gcc.target/riscv/arch-46.c | 5 +++++ 5 files changed, 20 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-46.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 4c9a72d1180..608f0950f0f 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -222,6 +222,8 @@ static const riscv_implied_info_t riscv_implied_info[] = {"sscofpmf", "zicsr"}, {"ssstateen", "zicsr"}, {"sstc", "zicsr"}, + {"ssdbltrp", "zicsr"}, + {"smdbltrp", "zicsr"}, {"xsfvcp", "zve32x"}, @@ -401,6 +403,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"sscofpmf", ISA_SPEC_CLASS_NONE, 1, 0}, {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0}, {"sstc", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ssdbltrp", ISA_SPEC_CLASS_NONE, 1, 0}, + {"smdbltrp", ISA_SPEC_CLASS_NONE, 1, 0}, {"svinval", ISA_SPEC_CLASS_NONE, 1, 0}, {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1725,6 +1729,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL), RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT), RISCV_EXT_FLAG_ENTRY ("svvptc", x_riscv_sv_subext, MASK_SVVPTC), + RISCV_EXT_FLAG_ENTRY ("ssdbltrp", x_riscv_sv_subext, MASK_SSDBLTRP), + RISCV_EXT_FLAG_ENTRY ("smdbltrp", x_riscv_sv_subext, MASK_SMDBLTRP), RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO), diff --git a/gcc/common/config/riscv/riscv-ext-bitmask.def b/gcc/common/config/riscv/riscv-ext-bitmask.def index a733533df98..9814b887b2d 100644 --- a/gcc/common/config/riscv/riscv-ext-bitmask.def +++ b/gcc/common/config/riscv/riscv-ext-bitmask.def @@ -80,5 +80,7 @@ RISCV_EXT_BITMASK ("zcf", 1, 5) RISCV_EXT_BITMASK ("zcmop", 1, 6) RISCV_EXT_BITMASK ("zawrs", 1, 7) RISCV_EXT_BITMASK ("svvptc", 1, 8) +RISCV_EXT_BITMASK ("ssdbltrp", 1, 9) +RISCV_EXT_BITMASK ("smdbltrp", 1, 10) #undef RISCV_EXT_BITMASK diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index a6a61a83db1..f5b3cf1103e 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -468,6 +468,8 @@ Mask(SVNAPOT) Var(riscv_sv_subext) Mask(SVVPTC) Var(riscv_sv_subext) +Mask(SSDBLTRP) Var(riscv_sv_subext) + TargetVariable int riscv_ztso_subext diff --git a/gcc/testsuite/gcc.target/riscv/arch-45.c b/gcc/testsuite/gcc.target/riscv/arch-45.c new file mode 100644 index 00000000000..85e2510b40a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-45.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_ssdbltrp -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-46.c b/gcc/testsuite/gcc.target/riscv/arch-46.c new file mode 100644 index 00000000000..85e2510b40a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-46.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_ssdbltrp -mabi=lp64" } */ +int foo() +{ +} -- 2.43.0
