Rename those constraint since we want define other constraint start with `c`, those constraints are internal and undocumented, so it's fine to rename.
gcc/ChangeLog: * config/riscv/constraints.md (c01): Rename to... (k01): ...this. (c02): Rename to... (k02): ...this. (c03): Rename to... (k03): ...this. (c04): Rename to... (k04): ...this. (c08): Rename to... (k08): ...this. * config/riscv/corev.md (riscv_cv_simd_add_h_si): Update constraints. (riscv_cv_simd_sub_h_si): Ditto. (riscv_cv_simd_cplxmul_i_si): Ditto. (riscv_cv_simd_subrotmj_si): Ditto. * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Update constraints. * config/riscv/vector-iterators.md (stride_load_constraint): Update constraints. (stride_store_constraint): Ditto. --- gcc/config/riscv/constraints.md | 10 +- gcc/config/riscv/corev.md | 10 +- gcc/config/riscv/riscv-v.cc | 2 +- gcc/config/riscv/vector-iterators.md | 444 +++++++++++++-------------- 4 files changed, 233 insertions(+), 233 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index eb5a0bb75c7..af8186117db 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -45,27 +45,27 @@ (define_constraint "J" (and (match_code "const_int") (match_test "ival == 0"))) -(define_constraint "c01" +(define_constraint "k01" "Constant value 1." (and (match_code "const_int") (match_test "ival == 1"))) -(define_constraint "c02" +(define_constraint "k02" "Constant value 2" (and (match_code "const_int") (match_test "ival == 2"))) -(define_constraint "c03" +(define_constraint "k03" "Constant value 3" (and (match_code "const_int") (match_test "ival == 3"))) -(define_constraint "c04" +(define_constraint "k04" "Constant value 4" (and (match_code "const_int") (match_test "ival == 4"))) -(define_constraint "c08" +(define_constraint "k08" "Constant value 8" (and (match_code "const_int") (match_test "ival == 8"))) diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md index e2db8f31130..02c27043301 100644 --- a/gcc/config/riscv/corev.md +++ b/gcc/config/riscv/corev.md @@ -871,7 +871,7 @@ (define_insn "riscv_cv_simd_add_h_si" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") (match_operand:SI 2 "register_operand" "r,r,r,r") - (match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")] + (match_operand:QI 3 "const_int2_operand" "J,k01,k02,k03")] UNSPEC_CV_ADD_H))] "TARGET_XCVSIMD && !TARGET_64BIT" "@ @@ -924,7 +924,7 @@ (define_insn "riscv_cv_simd_sub_h_si" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") (match_operand:SI 2 "register_operand" "r,r,r,r") - (match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")] + (match_operand:QI 3 "const_int2_operand" "J,k01,k02,k03")] UNSPEC_CV_SUB_H))] "TARGET_XCVSIMD && !TARGET_64BIT" "@ @@ -2561,7 +2561,7 @@ (define_insn "riscv_cv_simd_cplxmul_r_si" (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") (match_operand:SI 2 "register_operand" "r,r,r,r") (match_operand:SI 3 "register_operand" "0,0,0,0") - (match_operand:QI 4 "const_int2_operand" "J,c01,c02,c03")] + (match_operand:QI 4 "const_int2_operand" "J,k01,k02,k03")] UNSPEC_CV_CPLXMUL_R))] "TARGET_XCVSIMD && !TARGET_64BIT" "@ @@ -2578,7 +2578,7 @@ (define_insn "riscv_cv_simd_cplxmul_i_si" (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") (match_operand:SI 2 "register_operand" "r,r,r,r") (match_operand:SI 3 "register_operand" "0,0,0,0") - (match_operand:QI 4 "const_int2_operand" "J,c01,c02,c03")] + (match_operand:QI 4 "const_int2_operand" "J,k01,k02,k03")] UNSPEC_CV_CPLXMUL_I))] "TARGET_XCVSIMD && !TARGET_64BIT" "@ @@ -2604,7 +2604,7 @@ (define_insn "riscv_cv_simd_subrotmj_si" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") (match_operand:SI 2 "register_operand" "r,r,r,r") - (match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")] + (match_operand:QI 3 "const_int2_operand" "J,k01,k02,k03")] UNSPEC_CV_SUBROTMJ))] "TARGET_XCVSIMD && !TARGET_64BIT" "@ diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 47bc0255aa3..ebba33f82ca 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -5406,7 +5406,7 @@ splat_to_scalar_move_p (rtx *ops) return satisfies_constraint_Wc1 (ops[1]) && satisfies_constraint_vu (ops[2]) && !MEM_P (ops[3]) - && satisfies_constraint_c01 (ops[4]) + && satisfies_constraint_k01 (ops[4]) && INTVAL (ops[7]) == NONVLMAX && known_ge (GET_MODE_SIZE (Pmode), GET_MODE_SIZE (GET_MODE (ops[3]))); } diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 8e73022904b..dec5964edf2 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -3611,231 +3611,231 @@ (define_mode_attr stride_predicate [ ]) (define_mode_attr stride_load_constraint [ - (RVVM8QI "rJ,rJ,rJ,c01,c01,c01") (RVVM4QI "rJ,rJ,rJ,c01,c01,c01") - (RVVM2QI "rJ,rJ,rJ,c01,c01,c01") (RVVM1QI "rJ,rJ,rJ,c01,c01,c01") - (RVVMF2QI "rJ,rJ,rJ,c01,c01,c01") (RVVMF4QI "rJ,rJ,rJ,c01,c01,c01") - (RVVMF8QI "rJ,rJ,rJ,c01,c01,c01") - - (RVVM8HI "rJ,rJ,rJ,c02,c02,c02") (RVVM4HI "rJ,rJ,rJ,c02,c02,c02") - (RVVM2HI "rJ,rJ,rJ,c02,c02,c02") (RVVM1HI "rJ,rJ,rJ,c02,c02,c02") - (RVVMF2HI "rJ,rJ,rJ,c02,c02,c02") (RVVMF4HI "rJ,rJ,rJ,c02,c02,c02") - - (RVVM8BF "rJ,rJ,rJ,c02,c02,c02") (RVVM4BF "rJ,rJ,rJ,c02,c02,c02") - (RVVM2BF "rJ,rJ,rJ,c02,c02,c02") (RVVM1BF "rJ,rJ,rJ,c02,c02,c02") - (RVVMF2BF "rJ,rJ,rJ,c02,c02,c02") (RVVMF4BF "rJ,rJ,rJ,c02,c02,c02") - - (RVVM8HF "rJ,rJ,rJ,c02,c02,c02") (RVVM4HF "rJ,rJ,rJ,c02,c02,c02") - (RVVM2HF "rJ,rJ,rJ,c02,c02,c02") (RVVM1HF "rJ,rJ,rJ,c02,c02,c02") - (RVVMF2HF "rJ,rJ,rJ,c02,c02,c02") (RVVMF4HF "rJ,rJ,rJ,c02,c02,c02") - - (RVVM8SI "rJ,rJ,rJ,c04,c04,c04") (RVVM4SI "rJ,rJ,rJ,c04,c04,c04") - (RVVM2SI "rJ,rJ,rJ,c04,c04,c04") (RVVM1SI "rJ,rJ,rJ,c04,c04,c04") - (RVVMF2SI "rJ,rJ,rJ,c04,c04,c04") - - (RVVM8SF "rJ,rJ,rJ,c04,c04,c04") (RVVM4SF "rJ,rJ,rJ,c04,c04,c04") - (RVVM2SF "rJ,rJ,rJ,c04,c04,c04") (RVVM1SF "rJ,rJ,rJ,c04,c04,c04") - (RVVMF2SF "rJ,rJ,rJ,c04,c04,c04") - - (RVVM8DI "rJ,rJ,rJ,c08,c08,c08") (RVVM4DI "rJ,rJ,rJ,c08,c08,c08") - (RVVM2DI "rJ,rJ,rJ,c08,c08,c08") (RVVM1DI "rJ,rJ,rJ,c08,c08,c08") - - (RVVM8DF "rJ,rJ,rJ,c08,c08,c08") (RVVM4DF "rJ,rJ,rJ,c08,c08,c08") - (RVVM2DF "rJ,rJ,rJ,c08,c08,c08") (RVVM1DF "rJ,rJ,rJ,c08,c08,c08") - - (V1QI "rJ,rJ,rJ,c01,c01,c01") - (V2QI "rJ,rJ,rJ,c01,c01,c01") - (V4QI "rJ,rJ,rJ,c01,c01,c01") - (V8QI "rJ,rJ,rJ,c01,c01,c01") - (V16QI "rJ,rJ,rJ,c01,c01,c01") - (V32QI "rJ,rJ,rJ,c01,c01,c01") - (V64QI "rJ,rJ,rJ,c01,c01,c01") - (V128QI "rJ,rJ,rJ,c01,c01,c01") - (V256QI "rJ,rJ,rJ,c01,c01,c01") - (V512QI "rJ,rJ,rJ,c01,c01,c01") - (V1024QI "rJ,rJ,rJ,c01,c01,c01") - (V2048QI "rJ,rJ,rJ,c01,c01,c01") - (V4096QI "rJ,rJ,rJ,c01,c01,c01") - (V1HI "rJ,rJ,rJ,c02,c02,c02") - (V2HI "rJ,rJ,rJ,c02,c02,c02") - (V4HI "rJ,rJ,rJ,c02,c02,c02") - (V8HI "rJ,rJ,rJ,c02,c02,c02") - (V16HI "rJ,rJ,rJ,c02,c02,c02") - (V32HI "rJ,rJ,rJ,c02,c02,c02") - (V64HI "rJ,rJ,rJ,c02,c02,c02") - (V128HI "rJ,rJ,rJ,c02,c02,c02") - (V256HI "rJ,rJ,rJ,c02,c02,c02") - (V512HI "rJ,rJ,rJ,c02,c02,c02") - (V1024HI "rJ,rJ,rJ,c02,c02,c02") - (V2048HI "rJ,rJ,rJ,c02,c02,c02") - (V1SI "rJ,rJ,rJ,c04,c04,c04") - (V2SI "rJ,rJ,rJ,c04,c04,c04") - (V4SI "rJ,rJ,rJ,c04,c04,c04") - (V8SI "rJ,rJ,rJ,c04,c04,c04") - (V16SI "rJ,rJ,rJ,c04,c04,c04") - (V32SI "rJ,rJ,rJ,c04,c04,c04") - (V64SI "rJ,rJ,rJ,c04,c04,c04") - (V128SI "rJ,rJ,rJ,c04,c04,c04") - (V256SI "rJ,rJ,rJ,c04,c04,c04") - (V512SI "rJ,rJ,rJ,c04,c04,c04") - (V1024SI "rJ,rJ,rJ,c04,c04,c04") - (V1DI "rJ,rJ,rJ,c08,c08,c08") - (V2DI "rJ,rJ,rJ,c08,c08,c08") - (V4DI "rJ,rJ,rJ,c08,c08,c08") - (V8DI "rJ,rJ,rJ,c08,c08,c08") - (V16DI "rJ,rJ,rJ,c08,c08,c08") - (V32DI "rJ,rJ,rJ,c08,c08,c08") - (V64DI "rJ,rJ,rJ,c08,c08,c08") - (V128DI "rJ,rJ,rJ,c08,c08,c08") - (V256DI "rJ,rJ,rJ,c08,c08,c08") - (V512DI "rJ,rJ,rJ,c08,c08,c08") - - (V1HF "rJ,rJ,rJ,c02,c02,c02") - (V2HF "rJ,rJ,rJ,c02,c02,c02") - (V4HF "rJ,rJ,rJ,c02,c02,c02") - (V8HF "rJ,rJ,rJ,c02,c02,c02") - (V16HF "rJ,rJ,rJ,c02,c02,c02") - (V32HF "rJ,rJ,rJ,c02,c02,c02") - (V64HF "rJ,rJ,rJ,c02,c02,c02") - (V128HF "rJ,rJ,rJ,c02,c02,c02") - (V256HF "rJ,rJ,rJ,c02,c02,c02") - (V512HF "rJ,rJ,rJ,c02,c02,c02") - (V1024HF "rJ,rJ,rJ,c02,c02,c02") - (V2048HF "rJ,rJ,rJ,c02,c02,c02") - (V1SF "rJ,rJ,rJ,c04,c04,c04") - (V2SF "rJ,rJ,rJ,c04,c04,c04") - (V4SF "rJ,rJ,rJ,c04,c04,c04") - (V8SF "rJ,rJ,rJ,c04,c04,c04") - (V16SF "rJ,rJ,rJ,c04,c04,c04") - (V32SF "rJ,rJ,rJ,c04,c04,c04") - (V64SF "rJ,rJ,rJ,c04,c04,c04") - (V128SF "rJ,rJ,rJ,c04,c04,c04") - (V256SF "rJ,rJ,rJ,c04,c04,c04") - (V512SF "rJ,rJ,rJ,c04,c04,c04") - (V1024SF "rJ,rJ,rJ,c04,c04,c04") - (V1DF "rJ,rJ,rJ,c08,c08,c08") - (V2DF "rJ,rJ,rJ,c08,c08,c08") - (V4DF "rJ,rJ,rJ,c08,c08,c08") - (V8DF "rJ,rJ,rJ,c08,c08,c08") - (V16DF "rJ,rJ,rJ,c08,c08,c08") - (V32DF "rJ,rJ,rJ,c08,c08,c08") - (V64DF "rJ,rJ,rJ,c08,c08,c08") - (V128DF "rJ,rJ,rJ,c08,c08,c08") - (V256DF "rJ,rJ,rJ,c08,c08,c08") - (V512DF "rJ,rJ,rJ,c08,c08,c08") + (RVVM8QI "rJ,rJ,rJ,k01,k01,k01") (RVVM4QI "rJ,rJ,rJ,k01,k01,k01") + (RVVM2QI "rJ,rJ,rJ,k01,k01,k01") (RVVM1QI "rJ,rJ,rJ,k01,k01,k01") + (RVVMF2QI "rJ,rJ,rJ,k01,k01,k01") (RVVMF4QI "rJ,rJ,rJ,k01,k01,k01") + (RVVMF8QI "rJ,rJ,rJ,k01,k01,k01") + + (RVVM8HI "rJ,rJ,rJ,k02,k02,k02") (RVVM4HI "rJ,rJ,rJ,k02,k02,k02") + (RVVM2HI "rJ,rJ,rJ,k02,k02,k02") (RVVM1HI "rJ,rJ,rJ,k02,k02,k02") + (RVVMF2HI "rJ,rJ,rJ,k02,k02,k02") (RVVMF4HI "rJ,rJ,rJ,k02,k02,k02") + + (RVVM8BF "rJ,rJ,rJ,k02,k02,k02") (RVVM4BF "rJ,rJ,rJ,k02,k02,k02") + (RVVM2BF "rJ,rJ,rJ,k02,k02,k02") (RVVM1BF "rJ,rJ,rJ,k02,k02,k02") + (RVVMF2BF "rJ,rJ,rJ,k02,k02,k02") (RVVMF4BF "rJ,rJ,rJ,k02,k02,k02") + + (RVVM8HF "rJ,rJ,rJ,k02,k02,k02") (RVVM4HF "rJ,rJ,rJ,k02,k02,k02") + (RVVM2HF "rJ,rJ,rJ,k02,k02,k02") (RVVM1HF "rJ,rJ,rJ,k02,k02,k02") + (RVVMF2HF "rJ,rJ,rJ,k02,k02,k02") (RVVMF4HF "rJ,rJ,rJ,k02,k02,k02") + + (RVVM8SI "rJ,rJ,rJ,k04,k04,k04") (RVVM4SI "rJ,rJ,rJ,k04,k04,k04") + (RVVM2SI "rJ,rJ,rJ,k04,k04,k04") (RVVM1SI "rJ,rJ,rJ,k04,k04,k04") + (RVVMF2SI "rJ,rJ,rJ,k04,k04,k04") + + (RVVM8SF "rJ,rJ,rJ,k04,k04,k04") (RVVM4SF "rJ,rJ,rJ,k04,k04,k04") + (RVVM2SF "rJ,rJ,rJ,k04,k04,k04") (RVVM1SF "rJ,rJ,rJ,k04,k04,k04") + (RVVMF2SF "rJ,rJ,rJ,k04,k04,k04") + + (RVVM8DI "rJ,rJ,rJ,k08,k08,k08") (RVVM4DI "rJ,rJ,rJ,k08,k08,k08") + (RVVM2DI "rJ,rJ,rJ,k08,k08,k08") (RVVM1DI "rJ,rJ,rJ,k08,k08,k08") + + (RVVM8DF "rJ,rJ,rJ,k08,k08,k08") (RVVM4DF "rJ,rJ,rJ,k08,k08,k08") + (RVVM2DF "rJ,rJ,rJ,k08,k08,k08") (RVVM1DF "rJ,rJ,rJ,k08,k08,k08") + + (V1QI "rJ,rJ,rJ,k01,k01,k01") + (V2QI "rJ,rJ,rJ,k01,k01,k01") + (V4QI "rJ,rJ,rJ,k01,k01,k01") + (V8QI "rJ,rJ,rJ,k01,k01,k01") + (V16QI "rJ,rJ,rJ,k01,k01,k01") + (V32QI "rJ,rJ,rJ,k01,k01,k01") + (V64QI "rJ,rJ,rJ,k01,k01,k01") + (V128QI "rJ,rJ,rJ,k01,k01,k01") + (V256QI "rJ,rJ,rJ,k01,k01,k01") + (V512QI "rJ,rJ,rJ,k01,k01,k01") + (V1024QI "rJ,rJ,rJ,k01,k01,k01") + (V2048QI "rJ,rJ,rJ,k01,k01,k01") + (V4096QI "rJ,rJ,rJ,k01,k01,k01") + (V1HI "rJ,rJ,rJ,k02,k02,k02") + (V2HI "rJ,rJ,rJ,k02,k02,k02") + (V4HI "rJ,rJ,rJ,k02,k02,k02") + (V8HI "rJ,rJ,rJ,k02,k02,k02") + (V16HI "rJ,rJ,rJ,k02,k02,k02") + (V32HI "rJ,rJ,rJ,k02,k02,k02") + (V64HI "rJ,rJ,rJ,k02,k02,k02") + (V128HI "rJ,rJ,rJ,k02,k02,k02") + (V256HI "rJ,rJ,rJ,k02,k02,k02") + (V512HI "rJ,rJ,rJ,k02,k02,k02") + (V1024HI "rJ,rJ,rJ,k02,k02,k02") + (V2048HI "rJ,rJ,rJ,k02,k02,k02") + (V1SI "rJ,rJ,rJ,k04,k04,k04") + (V2SI "rJ,rJ,rJ,k04,k04,k04") + (V4SI "rJ,rJ,rJ,k04,k04,k04") + (V8SI "rJ,rJ,rJ,k04,k04,k04") + (V16SI "rJ,rJ,rJ,k04,k04,k04") + (V32SI "rJ,rJ,rJ,k04,k04,k04") + (V64SI "rJ,rJ,rJ,k04,k04,k04") + (V128SI "rJ,rJ,rJ,k04,k04,k04") + (V256SI "rJ,rJ,rJ,k04,k04,k04") + (V512SI "rJ,rJ,rJ,k04,k04,k04") + (V1024SI "rJ,rJ,rJ,k04,k04,k04") + (V1DI "rJ,rJ,rJ,k08,k08,k08") + (V2DI "rJ,rJ,rJ,k08,k08,k08") + (V4DI "rJ,rJ,rJ,k08,k08,k08") + (V8DI "rJ,rJ,rJ,k08,k08,k08") + (V16DI "rJ,rJ,rJ,k08,k08,k08") + (V32DI "rJ,rJ,rJ,k08,k08,k08") + (V64DI "rJ,rJ,rJ,k08,k08,k08") + (V128DI "rJ,rJ,rJ,k08,k08,k08") + (V256DI "rJ,rJ,rJ,k08,k08,k08") + (V512DI "rJ,rJ,rJ,k08,k08,k08") + + (V1HF "rJ,rJ,rJ,k02,k02,k02") + (V2HF "rJ,rJ,rJ,k02,k02,k02") + (V4HF "rJ,rJ,rJ,k02,k02,k02") + (V8HF "rJ,rJ,rJ,k02,k02,k02") + (V16HF "rJ,rJ,rJ,k02,k02,k02") + (V32HF "rJ,rJ,rJ,k02,k02,k02") + (V64HF "rJ,rJ,rJ,k02,k02,k02") + (V128HF "rJ,rJ,rJ,k02,k02,k02") + (V256HF "rJ,rJ,rJ,k02,k02,k02") + (V512HF "rJ,rJ,rJ,k02,k02,k02") + (V1024HF "rJ,rJ,rJ,k02,k02,k02") + (V2048HF "rJ,rJ,rJ,k02,k02,k02") + (V1SF "rJ,rJ,rJ,k04,k04,k04") + (V2SF "rJ,rJ,rJ,k04,k04,k04") + (V4SF "rJ,rJ,rJ,k04,k04,k04") + (V8SF "rJ,rJ,rJ,k04,k04,k04") + (V16SF "rJ,rJ,rJ,k04,k04,k04") + (V32SF "rJ,rJ,rJ,k04,k04,k04") + (V64SF "rJ,rJ,rJ,k04,k04,k04") + (V128SF "rJ,rJ,rJ,k04,k04,k04") + (V256SF "rJ,rJ,rJ,k04,k04,k04") + (V512SF "rJ,rJ,rJ,k04,k04,k04") + (V1024SF "rJ,rJ,rJ,k04,k04,k04") + (V1DF "rJ,rJ,rJ,k08,k08,k08") + (V2DF "rJ,rJ,rJ,k08,k08,k08") + (V4DF "rJ,rJ,rJ,k08,k08,k08") + (V8DF "rJ,rJ,rJ,k08,k08,k08") + (V16DF "rJ,rJ,rJ,k08,k08,k08") + (V32DF "rJ,rJ,rJ,k08,k08,k08") + (V64DF "rJ,rJ,rJ,k08,k08,k08") + (V128DF "rJ,rJ,rJ,k08,k08,k08") + (V256DF "rJ,rJ,rJ,k08,k08,k08") + (V512DF "rJ,rJ,rJ,k08,k08,k08") ]) (define_mode_attr stride_store_constraint [ - (RVVM8QI "rJ,c01") (RVVM4QI "rJ,c01") - (RVVM2QI "rJ,c01") (RVVM1QI "rJ,c01") - (RVVMF2QI "rJ,c01") (RVVMF4QI "rJ,c01") - (RVVMF8QI "rJ,c01") - - (RVVM8HI "rJ,c02") (RVVM4HI "rJ,c02") - (RVVM2HI "rJ,c02") (RVVM1HI "rJ,c02") - (RVVMF2HI "rJ,c02") (RVVMF4HI "rJ,c02") - - (RVVM8BF "rJ,c02") (RVVM4BF "rJ,c02") - (RVVM2BF "rJ,c02") (RVVM1BF "rJ,c02") - (RVVMF2BF "rJ,c02") (RVVMF4BF "rJ,c02") - - (RVVM8HF "rJ,c02") (RVVM4HF "rJ,c02") - (RVVM2HF "rJ,c02") (RVVM1HF "rJ,c02") - (RVVMF2HF "rJ,c02") (RVVMF4HF "rJ,c02") - - (RVVM8SI "rJ,c04") (RVVM4SI "rJ,c04") - (RVVM2SI "rJ,c04") (RVVM1SI "rJ,c04") - (RVVMF2SI "rJ,c04") - - (RVVM8SF "rJ,c04") (RVVM4SF "rJ,c04") - (RVVM2SF "rJ,c04") (RVVM1SF "rJ,c04") - (RVVMF2SF "rJ,c04") - - (RVVM8DI "rJ,c08") (RVVM4DI "rJ,c08") - (RVVM2DI "rJ,c08") (RVVM1DI "rJ,c08") - - (RVVM8DF "rJ,c08") (RVVM4DF "rJ,c08") - (RVVM2DF "rJ,c08") (RVVM1DF "rJ,c08") - - (V1QI "rJ,c01") - (V2QI "rJ,c01") - (V4QI "rJ,c01") - (V8QI "rJ,c01") - (V16QI "rJ,c01") - (V32QI "rJ,c01") - (V64QI "rJ,c01") - (V128QI "rJ,c01") - (V256QI "rJ,c01") - (V512QI "rJ,c01") - (V1024QI "rJ,c01") - (V2048QI "rJ,c01") - (V4096QI "rJ,c01") - (V1HI "rJ,c02") - (V2HI "rJ,c02") - (V4HI "rJ,c02") - (V8HI "rJ,c02") - (V16HI "rJ,c02") - (V32HI "rJ,c02") - (V64HI "rJ,c02") - (V128HI "rJ,c02") - (V256HI "rJ,c02") - (V512HI "rJ,c02") - (V1024HI "rJ,c02") - (V2048HI "rJ,c02") - (V1SI "rJ,c04") - (V2SI "rJ,c04") - (V4SI "rJ,c04") - (V8SI "rJ,c04") - (V16SI "rJ,c04") - (V32SI "rJ,c04") - (V64SI "rJ,c04") - (V128SI "rJ,c04") - (V256SI "rJ,c04") - (V512SI "rJ,c04") - (V1024SI "rJ,c04") - (V1DI "rJ,c08") - (V2DI "rJ,c08") - (V4DI "rJ,c08") - (V8DI "rJ,c08") - (V16DI "rJ,c08") - (V32DI "rJ,c08") - (V64DI "rJ,c08") - (V128DI "rJ,c08") - (V256DI "rJ,c08") - (V512DI "rJ,c08") - - (V1HF "rJ,c02") - (V2HF "rJ,c02") - (V4HF "rJ,c02") - (V8HF "rJ,c02") - (V16HF "rJ,c02") - (V32HF "rJ,c02") - (V64HF "rJ,c02") - (V128HF "rJ,c02") - (V256HF "rJ,c02") - (V512HF "rJ,c02") - (V1024HF "rJ,c02") - (V2048HF "rJ,c02") - (V1SF "rJ,c04") - (V2SF "rJ,c04") - (V4SF "rJ,c04") - (V8SF "rJ,c04") - (V16SF "rJ,c04") - (V32SF "rJ,c04") - (V64SF "rJ,c04") - (V128SF "rJ,c04") - (V256SF "rJ,c04") - (V512SF "rJ,c04") - (V1024SF "rJ,c04") - (V1DF "rJ,c08") - (V2DF "rJ,c08") - (V4DF "rJ,c08") - (V8DF "rJ,c08") - (V16DF "rJ,c08") - (V32DF "rJ,c08") - (V64DF "rJ,c08") - (V128DF "rJ,c08") - (V256DF "rJ,c08") - (V512DF "rJ,c08") + (RVVM8QI "rJ,k01") (RVVM4QI "rJ,k01") + (RVVM2QI "rJ,k01") (RVVM1QI "rJ,k01") + (RVVMF2QI "rJ,k01") (RVVMF4QI "rJ,k01") + (RVVMF8QI "rJ,k01") + + (RVVM8HI "rJ,k02") (RVVM4HI "rJ,k02") + (RVVM2HI "rJ,k02") (RVVM1HI "rJ,k02") + (RVVMF2HI "rJ,k02") (RVVMF4HI "rJ,k02") + + (RVVM8BF "rJ,k02") (RVVM4BF "rJ,k02") + (RVVM2BF "rJ,k02") (RVVM1BF "rJ,k02") + (RVVMF2BF "rJ,k02") (RVVMF4BF "rJ,k02") + + (RVVM8HF "rJ,k02") (RVVM4HF "rJ,k02") + (RVVM2HF "rJ,k02") (RVVM1HF "rJ,k02") + (RVVMF2HF "rJ,k02") (RVVMF4HF "rJ,k02") + + (RVVM8SI "rJ,k04") (RVVM4SI "rJ,k04") + (RVVM2SI "rJ,k04") (RVVM1SI "rJ,k04") + (RVVMF2SI "rJ,k04") + + (RVVM8SF "rJ,k04") (RVVM4SF "rJ,k04") + (RVVM2SF "rJ,k04") (RVVM1SF "rJ,k04") + (RVVMF2SF "rJ,k04") + + (RVVM8DI "rJ,k08") (RVVM4DI "rJ,k08") + (RVVM2DI "rJ,k08") (RVVM1DI "rJ,k08") + + (RVVM8DF "rJ,k08") (RVVM4DF "rJ,k08") + (RVVM2DF "rJ,k08") (RVVM1DF "rJ,k08") + + (V1QI "rJ,k01") + (V2QI "rJ,k01") + (V4QI "rJ,k01") + (V8QI "rJ,k01") + (V16QI "rJ,k01") + (V32QI "rJ,k01") + (V64QI "rJ,k01") + (V128QI "rJ,k01") + (V256QI "rJ,k01") + (V512QI "rJ,k01") + (V1024QI "rJ,k01") + (V2048QI "rJ,k01") + (V4096QI "rJ,k01") + (V1HI "rJ,k02") + (V2HI "rJ,k02") + (V4HI "rJ,k02") + (V8HI "rJ,k02") + (V16HI "rJ,k02") + (V32HI "rJ,k02") + (V64HI "rJ,k02") + (V128HI "rJ,k02") + (V256HI "rJ,k02") + (V512HI "rJ,k02") + (V1024HI "rJ,k02") + (V2048HI "rJ,k02") + (V1SI "rJ,k04") + (V2SI "rJ,k04") + (V4SI "rJ,k04") + (V8SI "rJ,k04") + (V16SI "rJ,k04") + (V32SI "rJ,k04") + (V64SI "rJ,k04") + (V128SI "rJ,k04") + (V256SI "rJ,k04") + (V512SI "rJ,k04") + (V1024SI "rJ,k04") + (V1DI "rJ,k08") + (V2DI "rJ,k08") + (V4DI "rJ,k08") + (V8DI "rJ,k08") + (V16DI "rJ,k08") + (V32DI "rJ,k08") + (V64DI "rJ,k08") + (V128DI "rJ,k08") + (V256DI "rJ,k08") + (V512DI "rJ,k08") + + (V1HF "rJ,k02") + (V2HF "rJ,k02") + (V4HF "rJ,k02") + (V8HF "rJ,k02") + (V16HF "rJ,k02") + (V32HF "rJ,k02") + (V64HF "rJ,k02") + (V128HF "rJ,k02") + (V256HF "rJ,k02") + (V512HF "rJ,k02") + (V1024HF "rJ,k02") + (V2048HF "rJ,k02") + (V1SF "rJ,k04") + (V2SF "rJ,k04") + (V4SF "rJ,k04") + (V8SF "rJ,k04") + (V16SF "rJ,k04") + (V32SF "rJ,k04") + (V64SF "rJ,k04") + (V128SF "rJ,k04") + (V256SF "rJ,k04") + (V512SF "rJ,k04") + (V1024SF "rJ,k04") + (V1DF "rJ,k08") + (V2DF "rJ,k08") + (V4DF "rJ,k08") + (V8DF "rJ,k08") + (V16DF "rJ,k08") + (V32DF "rJ,k08") + (V64DF "rJ,k08") + (V128DF "rJ,k08") + (V256DF "rJ,k08") + (V512DF "rJ,k08") ]) (define_mode_attr gs_extension [ -- 2.34.1