[PATCH v1 2/2] RISC-V: Adjust the strided store testcases check times on options

[pan2 . li]

From: Pan Li <pan2...@intel.com>

The vsse* dump check times changes on options (O2, O3) after we add
(mem:BLK (scratch)) to the define_insn of strided load.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Adjust
        the vsse check times based on optimization option.
        * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto.
        * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto.

Signed-off-by: Pan Li <pan2...@intel.com>
---
 .../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c | 3 ++-
 .../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c | 3 ++-
 .../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c | 3 ++-
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
index e4f6a40873b..2be8854a0b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
@@ -10,4 +10,5 @@ DEF_STRIDED_LD_ST_FORM_1(double)
 /* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { 
target { any-opts "-O2" } } } } */
 /* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { 
target { any-opts "-O2" } } } } */
 /* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 1 { target { any-opts "-O2" } 
} } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 2 { target { any-opts "-O3" } 
} } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
index afbce226368..13003e2ccdc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
@@ -10,4 +10,5 @@ DEF_STRIDED_LD_ST_FORM_1(int64_t)
 /* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { 
target { any-opts "-O2" } } } } */
 /* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { 
target { any-opts "-O2" } } } } */
 /* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 1 { target { any-opts "-O2" } 
} } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 2 { target { any-opts "-O3" } 
} } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
index a66eb5bcfd4..5df2caa793b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
@@ -10,4 +10,5 @@ DEF_STRIDED_LD_ST_FORM_1(uint64_t)
 /* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { 
target { any-opts "-O2" } } } } */
 /* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { 
target { any-opts "-O2" } } } } */
 /* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 1 { target { any-opts "-O2" } 
} } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 2 { target { any-opts "-O3" } 
} } } */
-- 
2.43.0