Re: [PATCH] RISC-V:Fix th.vsetvli generates from vext_x_v with wrong operand

[Robin Dapp]

> -      avl = GEN_INT (0);
> +      avl = TARGET_XTHEADVECTOR ? gen_rtx_REG(Pmode, 0) : GEN_INT (0);

Ah, the CI linter complains about a missing space after gen_rtx_REG.

-- 
Regards
 Robin