On 1/27/25 4:07 AM, pan2...@intel.com wrote:
From: Pan Li <pan2...@intel.com>
This patch would like to refactor the helper function of the SAT_*
scalar. The helper function will convert the define_pattern ops
to the xmode reg for the underlying code-gen. This patch add
new parameter for ZERO_EXTEND or SIGN_EXTEND if the input is const_int
or the mode is non-Xmode.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Rename from ...
(riscv_extend_to_xmode_reg): Rename to and add rtx_code for
zero/sign extend if non-Xmode.
(riscv_expand_usadd): Leverage the renamed function with ZERO_EXTEND.
(riscv_expand_ussub): Ditto.
Signed-off-by: Pan Li <pan2...@intel.com>
---
gcc/config/riscv/riscv.cc | 77 ++++++++++++++++++++++++---------------
1 file changed, 48 insertions(+), 29 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index dd50fe4eddf..34f0a888c5c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -12644,14 +12644,26 @@ riscv_get_raw_result_mode (int regno)
/* Generate a REG rtx of Xmode from the given rtx and mode.
The rtx x can be REG (QI/HI/SI/DI) or const_int.
The machine_mode mode is the original mode from define pattern.
+ The rtx_code can be ZERO_EXTEND or SIGN_EXTEND.
- If rtx is REG and Xmode, the RTX x will be returned directly.
+ If rtx is REG:
- If rtx is REG and non-Xmode, the zero extended to new REG of Xmode will be
- returned.
+ 1. If rtx Xmode, the RTX x will be returned directly.
+ 2. If rtx non-Xmode, the extended to new REG of Xmode will be returned.
I think you meant "the value extended into" rather than "the extended to".
OK with that fix.
Jeff
