On Thu, Feb 20, 2025 at 12:33 AM Dongyan Chen
<chendong...@isrc.iscas.ac.cn> wrote:
>
> This patch support Qualcomm uC Xqccmp extension[1].
> To enable GCC to recognize and process xqccmp extension correctly at compile
> time.
>
> [1]https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0
I am kinda of curious why you need this? Also is there a corresponding
binutils patch?
Please also CC myself (quic_apin...@quicinc.com) on all qualcomm
related GCC/GNU binutils patches.
Thanks,
Andrew Pinski
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc: New extension.
> * common/config/riscv/riscv-ext-bitmask.def (RISCV_EXT_BITMASK):
> Ditto.
> * config/riscv/riscv.opt: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-45.c: New test.
>
> ---
> gcc/common/config/riscv/riscv-common.cc | 6 ++++++
> gcc/common/config/riscv/riscv-ext-bitmask.def | 1 +
> gcc/config/riscv/riscv.opt | 5 +++++
> gcc/testsuite/gcc.target/riscv/arch-45.c | 5 +++++
> 4 files changed, 17 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc
> b/gcc/common/config/riscv/riscv-common.cc
> index 5038f0eb959a..6fbdb5ed2316 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -229,6 +229,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
>
> {"xsfvcp", "zve32x"},
>
> + {"xqccmp", "zca"},
> +
> {NULL, NULL}
> };
>
> @@ -442,6 +444,8 @@ static const struct riscv_ext_version
> riscv_ext_version_table[] =
> {"xsfvqmaccdod", ISA_SPEC_CLASS_NONE, 1, 0},
> {"xsfvfnrclipxfqf", ISA_SPEC_CLASS_NONE, 1, 0},
>
> + {"xqccmp", ISA_SPEC_CLASS_NONE, 0, 1},
> +
> /* Terminate the list. */
> {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
> };
> @@ -1778,6 +1782,8 @@ static const riscv_ext_flag_table_t
> riscv_ext_flag_table[] =
> RISCV_EXT_FLAG_ENTRY ("xsfvqmaccdod", x_riscv_sifive_subext,
> MASK_XSFVQMACCDOD),
> RISCV_EXT_FLAG_ENTRY ("xsfvfnrclipxfqf", x_riscv_sifive_subext,
> MASK_XSFVFNRCLIPXFQF),
>
> + RISCV_EXT_FLAG_ENTRY ("xqccmp", x_riscv_qc_subext, MASK_XQCCMP),
> +
> {NULL, NULL, NULL, 0}
> };
>
> diff --git a/gcc/common/config/riscv/riscv-ext-bitmask.def
> b/gcc/common/config/riscv/riscv-ext-bitmask.def
> index 8b4e6d6349a7..c2809460d582 100644
> --- a/gcc/common/config/riscv/riscv-ext-bitmask.def
> +++ b/gcc/common/config/riscv/riscv-ext-bitmask.def
> @@ -79,5 +79,6 @@ RISCV_EXT_BITMASK ("zcd", 1, 4)
> RISCV_EXT_BITMASK ("zcf", 1, 5)
> RISCV_EXT_BITMASK ("zcmop", 1, 6)
> RISCV_EXT_BITMASK ("zawrs", 1, 7)
> +RISCV_EXT_BITMASK ("xqccmp", 1, 8)
>
> #undef RISCV_EXT_BITMASK
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 7515c8ea13dd..61cc8258e323 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -535,6 +535,11 @@ Mask(XSFVQMACCDOD) Var(riscv_sifive_subext)
>
> Mask(XSFVFNRCLIPXFQF) Var(riscv_sifive_subext)
>
> +TargetVariable
> +int riscv_qc_subext
> +
> +Mask(XQCCMP) Var(riscv_qc_subext)
> +
> TargetVariable
> int riscv_fmv_priority = 0
>
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-45.c
> b/gcc/testsuite/gcc.target/riscv/arch-45.c
> new file mode 100644
> index 000000000000..590d4f130325
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-45.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_xqccmp -mabi=lp64" } */
> +int foo()
> +{
> +}
> --
> 2.43.0
>
