Some of these are harmless but still inconsistent (and asking for trouble
given it may give people the wrong idea about similar "style").
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/gen-attrs-6.C: Surround 'target' by whitespace.
* gcc.target/aarch64/atomic-inst-ldlogic.c: Fix 'dg-final' whitespace.
* gcc.target/arm/short-vfp-1.c: Ditto.
* gcc.target/bfin/l2.c: Fix 'dg-bfin-processors' whitespace.
* gcc.target/i386/avx512fp16-vmovw-1b.c: Surround 'target' by
whitespace.
* gcc.target/i386/sse2-float16-5.c: Ditto.
* gcc.target/powerpc/fold-vec-perm-longlong.c: Ditto.
---
gcc/testsuite/g++.dg/cpp0x/gen-attrs-6.C | 2 +-
gcc/testsuite/gcc.target/aarch64/atomic-inst-ldlogic.c | 4 ++--
gcc/testsuite/gcc.target/arm/short-vfp-1.c | 10 +++++-----
gcc/testsuite/gcc.target/bfin/l2.c | 2 +-
gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-1b.c | 2 +-
gcc/testsuite/gcc.target/i386/sse2-float16-5.c | 2 +-
.../gcc.target/powerpc/fold-vec-perm-longlong.c | 2 +-
7 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/gcc/testsuite/g++.dg/cpp0x/gen-attrs-6.C
b/gcc/testsuite/g++.dg/cpp0x/gen-attrs-6.C
index 54071d5ed149..d166add65b99 100644
--- a/gcc/testsuite/g++.dg/cpp0x/gen-attrs-6.C
+++ b/gcc/testsuite/g++.dg/cpp0x/gen-attrs-6.C
@@ -4,7 +4,7 @@
//
// Written by Richard Henderson, 26 May 2002.
-// { dg-do link { target c++11} }
+// { dg-do link { target c++11 } }
extern void foo [[gnu::nothrow]] ();
extern void link_error();
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-inst-ldlogic.c
b/gcc/testsuite/gcc.target/aarch64/atomic-inst-ldlogic.c
index 4879d52b9b4f..1927ebc10e28 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-inst-ldlogic.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-inst-ldlogic.c
@@ -128,7 +128,7 @@ TEST (xor_load_notreturn, XOR_LOAD_NORETURN)
/* { dg-final { scan-assembler-times "ldclrlh\t" 8} } */
/* { dg-final { scan-assembler-times "ldclralh\t" 16} } */
-/* { dg-final { scan-assembler-times "ldclr\t" 16} */
+/* { dg-final { scan-assembler-times "ldclr\t" 16 } */
/* { dg-final { scan-assembler-times "ldclra\t" 32} } */
/* { dg-final { scan-assembler-times "ldclrl\t" 16} } */
/* { dg-final { scan-assembler-times "ldclral\t" 32} } */
@@ -137,7 +137,7 @@ TEST (xor_load_notreturn, XOR_LOAD_NORETURN)
/* { dg-final { scan-assembler-times "ldeorb\t" 8} } */
/* { dg-final { scan-assembler-times "ldeorab\t" 16} } */
-/* { dg-final { scan-assembler-times "ldeorlb\t" 8} } */
+/* { dg-final { scan-assembler-times "ldeorlb\t" 8 } } */
/* { dg-final { scan-assembler-times "ldeoralb\t" 16} } */
/* { dg-final { scan-assembler-times "ldeorh\t" 8} } */
diff --git a/gcc/testsuite/gcc.target/arm/short-vfp-1.c
b/gcc/testsuite/gcc.target/arm/short-vfp-1.c
index 3ca1ffc00173..ddab09a4b7fb 100644
--- a/gcc/testsuite/gcc.target/arm/short-vfp-1.c
+++ b/gcc/testsuite/gcc.target/arm/short-vfp-1.c
@@ -38,8 +38,8 @@ test_sihi (short x)
return (int)x;
}
-/* {dg-final { scan-assembler-times {vcvt\.s32\.f32\ts[0-9]+,s[0-9]+} 2 }} */
-/* {dg-final { scan-assembler-times {vcvt\.f32\.s32\ts[0-9]+,s[0-9]+} 2 }} */
-/* {dg-final { scan-assembler-times {vmov\tr[0-9]+,s[0-9]+} 2 }} */
-/* {dg-final { scan-assembler-times {vmov\ts[0-9]+,r[0-9]+} 2 }} */
-/* {dg-final { scan-assembler-times {sxth\tr[0-9]+,r[0-9]+} 2 }} */
+/* { dg-final { scan-assembler-times {vcvt\.s32\.f32\ts[0-9]+,s[0-9]+} 2 }} */
+/* { dg-final { scan-assembler-times {vcvt\.f32\.s32\ts[0-9]+,s[0-9]+} 2 }} */
+/* { dg-final { scan-assembler-times {vmov\tr[0-9]+,s[0-9]+} 2 }} */
+/* { dg-final { scan-assembler-times {vmov\ts[0-9]+,r[0-9]+} 2 }} */
+/* { dg-final { scan-assembler-times {sxth\tr[0-9]+,r[0-9]+} 2 }} */
diff --git a/gcc/testsuite/gcc.target/bfin/l2.c
b/gcc/testsuite/gcc.target/bfin/l2.c
index 56f64cc82b48..2d39c46f8f12 100644
--- a/gcc/testsuite/gcc.target/bfin/l2.c
+++ b/gcc/testsuite/gcc.target/bfin/l2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target bfin-*-linux-uclibc } } */
-/* { dg-bfin-processors bf544 bf547 bf548 bf549 bf561} */
+/* { dg-bfin-processors bf544 bf547 bf548 bf549 bf561 } */
#if defined(__ADSPBF544__)
#define L2_START 0xFEB00000
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-1b.c
b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-1b.c
index a96007d6fd87..9b08f5a9c488 100644
--- a/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-1b.c
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-1b.c
@@ -1,4 +1,4 @@
-/* { dg-do run {target avx512fp16} } */
+/* { dg-do run { target avx512fp16 } } */
/* { dg-options "-O2 -mavx512fp16" } */
static void do_test (void);
diff --git a/gcc/testsuite/gcc.target/i386/sse2-float16-5.c
b/gcc/testsuite/gcc.target/i386/sse2-float16-5.c
index c3ed23b8ab3c..82078429cc20 100644
--- a/gcc/testsuite/gcc.target/i386/sse2-float16-5.c
+++ b/gcc/testsuite/gcc.target/i386/sse2-float16-5.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target ia32} } */
+/* { dg-do compile { target ia32 } } */
/* { dg-options "-O2 -mno-sse2" } */
_Float16 a;
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-longlong.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-longlong.c
index 06d6c1b1150e..4facb823adb3 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-longlong.c
@@ -1,7 +1,7 @@
/* Verify that overloaded built-ins for vec_perm with long long
inputs produce the right code. */
-/* { dg-do compile {target lp64} } */
+/* { dg-do compile { target lp64 } } */
// 'long long' in Altivec types is invalid without -mvsx.
/* { dg-options "-mvsx -O2" } */
/* { dg-require-effective-target powerpc_vsx } */
--
2.49.0
