Hi Jeff, On Fri, Apr 25, 2025 at 6:04 AM Jeff Law <jeffreya...@gmail.com> wrote: > > On 4/24/25 2:37 AM, Anton Blanchard wrote: > > Add integer and floating point scheduling models for the Tenstorrent > > Ascalon 8 wide CPU. > > > > gcc/ChangeLog: > > * config/riscv/riscv-cores.def (RISCV_TUNE): Update. > > * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): > > Add tt_ascalon_d8. > > * config/riscv/riscv.md: Update tune attribute and include > > tt-ascalon-d8.md. > > * config/riscv/tenstorrent-ascalon.md: New file. > This looks pretty sensible. The only worry would be insns types that > don't have a mapping to anything in the DFA -- those will cause an ICE > in the scheduler as we require all insns to have a type and map to a > reservation in the DFA. > > So for example someone could ask for rv64gcv code generation, but > ascalon-d8 scheduling. The compiler will ultimately fault in the > scheduler because you don't have a mapping of vector insns to a > reservation in the DFA.
Thanks for the review. I was able to build cpu2006 with -mcpu=rv64gcv -mtune=tt-ascalon-d8. I think this is because the generic-vector-ooo description doesn't check tune so is applied always. Thanks, Anton
