On Mon, 5 May 2025, 09:53 Jonathan Wakely, <jwakely....@gmail.com> wrote:
>
>
> On Mon, 5 May 2025, 09:23 Sam James, <s...@gentoo.org> wrote:
>
>> Jonathan Wakely <jwak...@redhat.com> writes:
>>
>> > [...]
>> > +void
>> > +std::breakpoint() noexcept
>> > +{
>> > + PROBE(std::breakpoint);
>> > +
>> > + if (__gnu_cxx::debugger_signal_for_breakpoint > 0)
>> > + std::raise(__gnu_cxx::debugger_signal_for_breakpoint);
>> > +
>>
>> glib's
>> https://gitlab.gnome.org/GNOME/glib/-/blob/main/glib/gbacktrace.h#L58 is
>> a useful reference. It has an entry for alpha and also MSVC (though I
>> can't imagine MSVC matters here).
>>
>
> I can't load that page, Anubis takes 10s then I get "invalid response".
>
It worked after about a dozen attempts.
>
>
>> > +#if _GLIBCXX_HAVE_DEBUGAPI_H && defined(_WIN32) && !defined(__CYGWIN__)
>> > + DebugBreak();
>> > +#elif __has_builtin(__builtin_debugtrap)
>> > + __builtin_debugtrap(); // Clang
>> > +#elif defined(__i386__) || defined(__x86_64__)
>> > + __asm__ volatile ("int3; nop");
>> > +#elifdef __thumb__
>> > + __asm__ volatile (".inst 0xde01");
>> > +#elifdef __aarch64__
>> > + __asm__ volatile (".inst 0xd4200000");
>> > +#elifdef __arm__
>> > + __asm__ volatile (".inst 0xe7f001f0");
>> > +#elifdef __riscv
>> > + /* section 2.8 in the RISC-V unprivileged ISA manual says for
>> semi-hosted
>> > + * environments we want the sequence:
>> > + * slli x0, x0, 0x1f # Entry NOP
>> > + * ebreak # Break to debugger
>> > + * srai x0, x0, 7 # NOP encoding the semihosting call number 7
>> > + */
>> > + __asm__ volatile (".4byte 0x00100073");
>> > +#elifdef __powerpc__
>> > + __asm__ volatile(".4byte 0x7d821008");
>> > +#else
>> > + __builtin_trap();
>> > +#endif
>> > +} // If the debugger stops here, std::breakpoint() was called.
>> > +
>> > [...]
>>
>
