From: Soumya AR <soum...@nvidia.com>
To allow runtime updates to tuning parameters, the const keyword is removed
from aarch64 tune_params and all its nested structures and structure members.
Since this patch also touches tuning structures in the arm backend, it was
bootstrapped on aarch64-linux-gnu as well as arm-linux-gnueabihf.
Signed-off-by: Soumya AR <soum...@nvidia.com>
gcc/ChangeLog:
* config/aarch64/aarch64-cost-tables.h (struct cpu_cost_table): Remove
const keyword.
* config/aarch64/aarch64-protos.h (struct scale_addr_mode_cost):
Likewise.
(struct cpu_addrcost_table): Likewise.
(struct cpu_regmove_cost): Likewise.
(struct simd_vec_cost): Likewise.
(struct sve_vec_cost): Likewise.
(struct aarch64_base_vec_issue_info): Likewise.
(struct aarch64_simd_vec_issue_info): Likewise.
(struct aarch64_sve_vec_issue_info): Likewise.
(struct aarch64_vec_issue_info): Likewise.
(struct cpu_vector_cost): Likewise.
(struct cpu_branch_cost): Likewise.
(struct cpu_approx_modes): Likewise.
(struct cpu_prefetch_tune): Likewise.
(struct tune_params): Likewise.
* config/aarch64/aarch64.cc (aarch64_rtx_mult_cost): Likewise.
(aarch64_branch_cost): Likewise.
(aarch64_if_then_else_costs): Likewise.
(aarch64_rtx_costs): Likewise.
(aarch64_vec_op_count): Likewise.
(aarch64_vec_op_count::simd_issue_info): Likewise.
(aarch64_simd_vec_costs): Likewise.
(aarch64_simd_vec_costs_for_flags): Likewise.
(aarch64_builtin_vectorization_cost): Likewise.
(aarch64_sve_in_loop_reduction_latency): Likewise.
(aarch64_in_loop_reduction_latency): Likewise.
(aarch64_detect_vector_stmt_subtype): Likewise.
(aarch64_vector_costs::count_ops): Likewise.
(aarch64_vector_costs::add_stmt_cost): Likewise.
* config/aarch64/tuning_models/a64fx.h: Likewise.
* config/aarch64/tuning_models/ampere1.h: Likewise.
* config/aarch64/tuning_models/ampere1a.h: Likewise.
* config/aarch64/tuning_models/ampere1b.h: Likewise.
* config/aarch64/tuning_models/cortexa35.h: Likewise.
* config/aarch64/tuning_models/cortexa53.h: Likewise.
* config/aarch64/tuning_models/cortexa57.h: Likewise.
* config/aarch64/tuning_models/cortexa72.h: Likewise.
* config/aarch64/tuning_models/cortexa73.h: Likewise.
* config/aarch64/tuning_models/cortexx925.h: Likewise.
* config/aarch64/tuning_models/emag.h: Likewise.
* config/aarch64/tuning_models/exynosm1.h: Likewise.
* config/aarch64/tuning_models/fujitsu_monaka.h: Likewise.
* config/aarch64/tuning_models/generic.h: Likewise.
* config/aarch64/tuning_models/generic_armv8_a.h: Likewise.
* config/aarch64/tuning_models/generic_armv9_a.h: Likewise.
* config/aarch64/tuning_models/neoverse512tvb.h: Likewise.
* config/aarch64/tuning_models/neoversen1.h: Likewise.
* config/aarch64/tuning_models/neoversen2.h: Likewise.
* config/aarch64/tuning_models/neoversen3.h: Likewise.
* config/aarch64/tuning_models/neoversev1.h: Likewise.
* config/aarch64/tuning_models/neoversev2.h: Likewise.
* config/aarch64/tuning_models/neoversev3.h: Likewise.
* config/aarch64/tuning_models/neoversev3ae.h: Likewise.
* config/aarch64/tuning_models/qdf24xx.h: Likewise.
* config/aarch64/tuning_models/saphira.h: Likewise.
* config/aarch64/tuning_models/thunderx.h: Likewise.
* config/aarch64/tuning_models/thunderx2t99.h: Likewise.
* config/aarch64/tuning_models/thunderx3t110.h: Likewise.
* config/aarch64/tuning_models/thunderxt88.h: Likewise.
* config/aarch64/tuning_models/tsv110.h: Likewise.
* config/aarch64/tuning_models/xgene1.h: Likewise.
* config/arm/aarch-common-protos.h (struct alu_cost_table): Likewise.
(struct mult_cost_table): Likewise.
(struct mem_cost_table): Likewise.
(struct fp_cost_table): Likewise.
(struct vector_cost_table): Likewise.
(struct cpu_cost_table): Likewise.
* config/arm/aarch-cost-tables.h (struct cpu_cost_table): Likewise.
* config/arm/arm-protos.h (struct tune_params): Likewise.
* config/arm/arm.cc (struct cpu_cost_table): Likewise.
(arm_unspec_cost): Likewise.
(arm_mem_costs): Likewise.
(arm_rtx_costs_internal): Likewise.
---
gcc/config/aarch64/aarch64-cost-tables.h | 18 +-
gcc/config/aarch64/aarch64-protos.h | 182 +++++++++---------
gcc/config/aarch64/aarch64.cc | 36 ++--
gcc/config/aarch64/tuning_models/a64fx.h | 14 +-
gcc/config/aarch64/tuning_models/ampere1.h | 8 +-
gcc/config/aarch64/tuning_models/ampere1a.h | 2 +-
gcc/config/aarch64/tuning_models/ampere1b.h | 8 +-
gcc/config/aarch64/tuning_models/cortexa35.h | 2 +-
gcc/config/aarch64/tuning_models/cortexa53.h | 4 +-
gcc/config/aarch64/tuning_models/cortexa57.h | 8 +-
gcc/config/aarch64/tuning_models/cortexa72.h | 2 +-
gcc/config/aarch64/tuning_models/cortexa73.h | 2 +-
gcc/config/aarch64/tuning_models/cortexx925.h | 18 +-
gcc/config/aarch64/tuning_models/emag.h | 2 +-
gcc/config/aarch64/tuning_models/exynosm1.h | 14 +-
.../aarch64/tuning_models/fujitsu_monaka.h | 2 +-
gcc/config/aarch64/tuning_models/generic.h | 18 +-
.../aarch64/tuning_models/generic_armv8_a.h | 18 +-
.../aarch64/tuning_models/generic_armv9_a.h | 22 +--
.../aarch64/tuning_models/neoverse512tvb.h | 10 +-
gcc/config/aarch64/tuning_models/neoversen1.h | 2 +-
gcc/config/aarch64/tuning_models/neoversen2.h | 18 +-
gcc/config/aarch64/tuning_models/neoversen3.h | 18 +-
gcc/config/aarch64/tuning_models/neoversev1.h | 20 +-
gcc/config/aarch64/tuning_models/neoversev2.h | 18 +-
gcc/config/aarch64/tuning_models/neoversev3.h | 18 +-
.../aarch64/tuning_models/neoversev3ae.h | 18 +-
gcc/config/aarch64/tuning_models/qdf24xx.h | 12 +-
gcc/config/aarch64/tuning_models/saphira.h | 2 +-
gcc/config/aarch64/tuning_models/thunderx.h | 10 +-
.../aarch64/tuning_models/thunderx2t99.h | 12 +-
.../aarch64/tuning_models/thunderx3t110.h | 12 +-
.../aarch64/tuning_models/thunderxt88.h | 4 +-
gcc/config/aarch64/tuning_models/tsv110.h | 12 +-
gcc/config/aarch64/tuning_models/xgene1.h | 14 +-
gcc/config/arm/aarch-common-protos.h | 128 ++++++------
gcc/config/arm/aarch-cost-tables.h | 12 +-
gcc/config/arm/arm-protos.h | 2 +-
gcc/config/arm/arm.cc | 20 +-
39 files changed, 371 insertions(+), 371 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-cost-tables.h
b/gcc/config/aarch64/aarch64-cost-tables.h
index c49ff7f62ef..a12467b74ac 100644
--- a/gcc/config/aarch64/aarch64-cost-tables.h
+++ b/gcc/config/aarch64/aarch64-cost-tables.h
@@ -24,7 +24,7 @@
#include "config/arm/aarch-cost-tables.h"
/* QDF24xx does not implement AArch32. */
-const struct cpu_cost_table qdf24xx_extra_costs =
+struct cpu_cost_table qdf24xx_extra_costs =
{
/* ALU */
{
@@ -132,7 +132,7 @@ const struct cpu_cost_table qdf24xx_extra_costs =
};
/* ThunderX does not implement AArch32. */
-const struct cpu_cost_table thunderx_extra_costs =
+struct cpu_cost_table thunderx_extra_costs =
{
/* ALU */
{
@@ -239,7 +239,7 @@ const struct cpu_cost_table thunderx_extra_costs =
}
};
-const struct cpu_cost_table thunderx2t99_extra_costs =
+struct cpu_cost_table thunderx2t99_extra_costs =
{
/* ALU */
{
@@ -346,7 +346,7 @@ const struct cpu_cost_table thunderx2t99_extra_costs =
}
};
-const struct cpu_cost_table thunderx3t110_extra_costs =
+struct cpu_cost_table thunderx3t110_extra_costs =
{
/* ALU */
{
@@ -453,7 +453,7 @@ const struct cpu_cost_table thunderx3t110_extra_costs =
}
};
-const struct cpu_cost_table tsv110_extra_costs =
+struct cpu_cost_table tsv110_extra_costs =
{
/* ALU */
{
@@ -561,7 +561,7 @@ const struct cpu_cost_table tsv110_extra_costs =
}
};
-const struct cpu_cost_table a64fx_extra_costs =
+struct cpu_cost_table a64fx_extra_costs =
{
/* ALU */
{
@@ -668,7 +668,7 @@ const struct cpu_cost_table a64fx_extra_costs =
}
};
-const struct cpu_cost_table ampere1_extra_costs =
+struct cpu_cost_table ampere1_extra_costs =
{
/* ALU */
{
@@ -775,7 +775,7 @@ const struct cpu_cost_table ampere1_extra_costs =
}
};
-const struct cpu_cost_table ampere1a_extra_costs =
+struct cpu_cost_table ampere1a_extra_costs =
{
/* ALU */
{
@@ -882,7 +882,7 @@ const struct cpu_cost_table ampere1a_extra_costs =
}
};
-const struct cpu_cost_table ampere1b_extra_costs =
+struct cpu_cost_table ampere1b_extra_costs =
{
/* ALU */
{
diff --git a/gcc/config/aarch64/aarch64-protos.h
b/gcc/config/aarch64/aarch64-protos.h
index 4235f4a0ca5..e92f622e167 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -166,88 +166,88 @@ enum aarch64_salt_type {
struct scale_addr_mode_cost
{
- const int hi;
- const int si;
- const int di;
- const int ti;
+ int hi;
+ int si;
+ int di;
+ int ti;
};
/* Additional cost for addresses. */
struct cpu_addrcost_table
{
- const struct scale_addr_mode_cost addr_scale_costs;
- const int pre_modify;
- const int post_modify;
- const int post_modify_ld3_st3;
- const int post_modify_ld4_st4;
- const int register_offset;
- const int register_sextend;
- const int register_zextend;
- const int imm_offset;
+ struct scale_addr_mode_cost addr_scale_costs;
+ int pre_modify;
+ int post_modify;
+ int post_modify_ld3_st3;
+ int post_modify_ld4_st4;
+ int register_offset;
+ int register_sextend;
+ int register_zextend;
+ int imm_offset;
};
/* Additional costs for register copies. Cost is for one register. */
struct cpu_regmove_cost
{
- const int GP2GP;
- const int GP2FP;
- const int FP2GP;
- const int FP2FP;
+ int GP2GP;
+ int GP2FP;
+ int FP2GP;
+ int FP2FP;
};
struct simd_vec_cost
{
/* Cost of any integer vector operation, excluding the ones handled
specially below. */
- const int int_stmt_cost;
+ int int_stmt_cost;
/* Cost of any fp vector operation, excluding the ones handled
specially below. */
- const int fp_stmt_cost;
+ int fp_stmt_cost;
/* Per-vector cost of permuting vectors after an LD2, LD3 or LD4,
as well as the per-vector cost of permuting vectors before
an ST2, ST3 or ST4. */
- const int ld2_st2_permute_cost;
- const int ld3_st3_permute_cost;
- const int ld4_st4_permute_cost;
+ int ld2_st2_permute_cost;
+ int ld3_st3_permute_cost;
+ int ld4_st4_permute_cost;
/* Cost of a permute operation. */
- const int permute_cost;
+ int permute_cost;
/* Cost of reductions for various vector types: iN is for N-bit
integer elements and fN is for N-bit floating-point elements.
We need to single out the element type because it affects the
depth of the reduction. */
- const int reduc_i8_cost;
- const int reduc_i16_cost;
- const int reduc_i32_cost;
- const int reduc_i64_cost;
- const int reduc_f16_cost;
- const int reduc_f32_cost;
- const int reduc_f64_cost;
+ int reduc_i8_cost;
+ int reduc_i16_cost;
+ int reduc_i32_cost;
+ int reduc_i64_cost;
+ int reduc_f16_cost;
+ int reduc_f32_cost;
+ int reduc_f64_cost;
/* Additional cost of storing a single vector element, on top of the
normal cost of a scalar store. */
- const int store_elt_extra_cost;
+ int store_elt_extra_cost;
/* Cost of a vector-to-scalar operation. */
- const int vec_to_scalar_cost;
+ int vec_to_scalar_cost;
/* Cost of a scalar-to-vector operation. */
- const int scalar_to_vec_cost;
+ int scalar_to_vec_cost;
/* Cost of an aligned vector load. */
- const int align_load_cost;
+ int align_load_cost;
/* Cost of an unaligned vector load. */
- const int unalign_load_cost;
+ int unalign_load_cost;
/* Cost of an unaligned vector store. */
- const int unalign_store_cost;
+ int unalign_store_cost;
/* Cost of a vector store. */
- const int store_cost;
+ int store_cost;
};
typedef struct simd_vec_cost advsimd_vec_cost;
@@ -280,27 +280,27 @@ struct sve_vec_cost : simd_vec_cost
/* The cost of a vector-to-scalar CLASTA or CLASTB instruction,
with the scalar being stored in FP registers. This cost is
assumed to be a cycle latency. */
- const int clast_cost;
+ int clast_cost;
/* The costs of FADDA for the three data types that it supports.
These costs are assumed to be cycle latencies. */
- const int fadda_f16_cost;
- const int fadda_f32_cost;
- const int fadda_f64_cost;
+ int fadda_f16_cost;
+ int fadda_f32_cost;
+ int fadda_f64_cost;
/* The cost of a gather load instruction. The x32 value is for loads
of 32-bit elements and the x64 value is for loads of 64-bit elements. */
- const int gather_load_x32_cost;
- const int gather_load_x64_cost;
+ int gather_load_x32_cost;
+ int gather_load_x64_cost;
/* Additional loop initialization cost of using a gather load instruction.
The x32
value is for loads of 32-bit elements and the x64 value is for loads of
64-bit elements. */
- const int gather_load_x32_init_cost;
- const int gather_load_x64_init_cost;
+ int gather_load_x32_init_cost;
+ int gather_load_x64_init_cost;
/* The per-element cost of a scatter store. */
- const int scatter_store_elt_cost;
+ int scatter_store_elt_cost;
};
/* Base information about how the CPU issues code, containing
@@ -319,10 +319,10 @@ struct sve_vec_cost : simd_vec_cost
struct aarch64_base_vec_issue_info
{
/* How many loads and stores can be issued per cycle. */
- const unsigned int loads_stores_per_cycle;
+ unsigned int loads_stores_per_cycle;
/* How many stores can be issued per cycle. */
- const unsigned int stores_per_cycle;
+ unsigned int stores_per_cycle;
/* How many integer or FP/SIMD operations can be issued per cycle.
@@ -338,7 +338,7 @@ struct aarch64_base_vec_issue_info
This is not very precise, but it's only meant to be a heuristic.
We could certainly try to do better in future if there's an example
of something that would benefit. */
- const unsigned int general_ops_per_cycle;
+ unsigned int general_ops_per_cycle;
/* How many FP/SIMD operations to count for a floating-point or
vector load operation.
@@ -347,7 +347,7 @@ struct aarch64_base_vec_issue_info
been loaded from memory, these values apply to each individual load.
When using an SVE gather load, the values apply to each element of
the gather. */
- const unsigned int fp_simd_load_general_ops;
+ unsigned int fp_simd_load_general_ops;
/* How many FP/SIMD operations to count for a floating-point or
vector store operation.
@@ -355,7 +355,7 @@ struct aarch64_base_vec_issue_info
When storing individual elements of an Advanced SIMD vector out to
memory, these values apply to each individual store. When using an
SVE scatter store, these values apply to each element of the scatter. */
- const unsigned int fp_simd_store_general_ops;
+ unsigned int fp_simd_store_general_ops;
};
using aarch64_scalar_vec_issue_info = aarch64_base_vec_issue_info;
@@ -382,9 +382,9 @@ struct aarch64_simd_vec_issue_info :
aarch64_base_vec_issue_info
load ops: 3
general ops: 3 * (fp_simd_load_general_ops + ld3_st3_general_ops). */
- const unsigned int ld2_st2_general_ops;
- const unsigned int ld3_st3_general_ops;
- const unsigned int ld4_st4_general_ops;
+ unsigned int ld2_st2_general_ops;
+ unsigned int ld3_st3_general_ops;
+ unsigned int ld4_st4_general_ops;
};
using aarch64_advsimd_vec_issue_info = aarch64_simd_vec_issue_info;
@@ -411,19 +411,19 @@ struct aarch64_sve_vec_issue_info :
aarch64_simd_vec_issue_info
{}
/* How many predicate operations can be issued per cycle. */
- const unsigned int pred_ops_per_cycle;
+ unsigned int pred_ops_per_cycle;
/* How many predicate operations are generated by a WHILExx
instruction. */
- const unsigned int while_pred_ops;
+ unsigned int while_pred_ops;
/* How many predicate operations are generated by an integer
comparison instruction. */
- const unsigned int int_cmp_pred_ops;
+ unsigned int int_cmp_pred_ops;
/* How many predicate operations are generated by a floating-point
comparison instruction. */
- const unsigned int fp_cmp_pred_ops;
+ unsigned int fp_cmp_pred_ops;
/* How many general and predicate operations are generated by each pair
of elements in a gather load or scatter store. These values apply
@@ -433,54 +433,54 @@ struct aarch64_sve_vec_issue_info :
aarch64_simd_vec_issue_info
The reason for using pairs is that that is the largest possible
granule size for 128-bit SVE, which can load and store 2 64-bit
elements or 4 32-bit elements. */
- const unsigned int gather_scatter_pair_general_ops;
- const unsigned int gather_scatter_pair_pred_ops;
+ unsigned int gather_scatter_pair_general_ops;
+ unsigned int gather_scatter_pair_pred_ops;
};
/* Information related to instruction issue for a particular CPU. */
struct aarch64_vec_issue_info
{
- const aarch64_base_vec_issue_info *const scalar;
- const aarch64_simd_vec_issue_info *const advsimd;
- const aarch64_sve_vec_issue_info *const sve;
+ aarch64_base_vec_issue_info *scalar;
+ aarch64_simd_vec_issue_info *advsimd;
+ aarch64_sve_vec_issue_info *sve;
};
/* Cost for vector insn classes. */
struct cpu_vector_cost
{
/* Cost of any integer scalar operation, excluding load and store. */
- const int scalar_int_stmt_cost;
+ int scalar_int_stmt_cost;
/* Cost of any fp scalar operation, excluding load and store. */
- const int scalar_fp_stmt_cost;
+ int scalar_fp_stmt_cost;
/* Cost of a scalar load. */
- const int scalar_load_cost;
+ int scalar_load_cost;
/* Cost of a scalar store. */
- const int scalar_store_cost;
+ int scalar_store_cost;
/* Cost of a taken branch. */
- const int cond_taken_branch_cost;
+ int cond_taken_branch_cost;
/* Cost of a not-taken branch. */
- const int cond_not_taken_branch_cost;
+ int cond_not_taken_branch_cost;
/* Cost of an Advanced SIMD operations. */
- const advsimd_vec_cost *advsimd;
+ advsimd_vec_cost *advsimd;
/* Cost of an SVE operations, or null if SVE is not implemented. */
- const sve_vec_cost *sve;
+ sve_vec_cost *sve;
/* Issue information, or null if none is provided. */
- const aarch64_vec_issue_info *const issue_info;
+ aarch64_vec_issue_info *const issue_info;
};
/* Branch costs. */
struct cpu_branch_cost
{
- const int predictable; /* Predictable branch or optimizing for size. */
- const int unpredictable; /* Unpredictable branch or optimizing for speed.
*/
+ int predictable; /* Predictable branch or optimizing for size. */
+ int unpredictable; /* Unpredictable branch or optimizing for speed. */
};
/* Control approximate alternatives to certain FP operators. */
@@ -497,25 +497,25 @@ struct cpu_branch_cost
/* Allowed modes for approximations. */
struct cpu_approx_modes
{
- const uint64_t division; /* Division. */
- const uint64_t sqrt; /* Square root. */
- const uint64_t recip_sqrt; /* Reciprocal square root. */
+ uint64_t division; /* Division. */
+ uint64_t sqrt; /* Square root. */
+ uint64_t recip_sqrt; /* Reciprocal square root. */
};
/* Cache prefetch settings for prefetch-loop-arrays. */
struct cpu_prefetch_tune
{
- const int num_slots;
- const int l1_cache_size;
- const int l1_cache_line_size;
- const int l2_cache_size;
+ int num_slots;
+ int l1_cache_size;
+ int l1_cache_line_size;
+ int l2_cache_size;
/* Whether software prefetch hints should be issued for non-constant
strides. */
- const bool prefetch_dynamic_strides;
+ bool prefetch_dynamic_strides;
/* The minimum constant stride beyond which we should use prefetch
hints for. */
- const int minimum_stride;
- const int default_opt_level;
+ int minimum_stride;
+ int default_opt_level;
};
/* Model the costs for loads/stores for the register allocators so that it can
@@ -532,12 +532,12 @@ struct cpu_memmov_cost
struct tune_params
{
- const struct cpu_cost_table *insn_extra_cost;
- const struct cpu_addrcost_table *addr_cost;
- const struct cpu_regmove_cost *regmove_cost;
- const struct cpu_vector_cost *vec_costs;
- const struct cpu_branch_cost *branch_costs;
- const struct cpu_approx_modes *approx_modes;
+ struct cpu_cost_table *insn_extra_cost;
+ struct cpu_addrcost_table *addr_cost;
+ struct cpu_regmove_cost *regmove_cost;
+ struct cpu_vector_cost *vec_costs;
+ struct cpu_branch_cost *branch_costs;
+ struct cpu_approx_modes *approx_modes;
/* A bitmask of the possible SVE register widths in bits,
or SVE_NOT_IMPLEMENTED if not applicable. Only used for tuning
decisions, does not disable VLA vectorization. */
@@ -577,7 +577,7 @@ struct tune_params
/* Place prefetch struct pointer at the end to enable type checking
errors when tune_params misses elements (e.g., from erroneous merges). */
- const struct cpu_prefetch_tune *prefetch;
+ struct cpu_prefetch_tune *prefetch;
/* Define models for the aarch64_ldp_stp_policy. */
enum aarch64_ldp_stp_policy ldp_policy_model, stp_policy_model;
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 4586f22a9b9..f9d56eea7ee 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -13791,7 +13791,7 @@ static int
aarch64_rtx_mult_cost (rtx x, enum rtx_code code, int outer, bool speed)
{
rtx op0, op1;
- const struct cpu_cost_table *extra_cost
+ struct cpu_cost_table *extra_cost
= aarch64_tune_params.insn_extra_cost;
int cost = 0;
bool compound_p = (outer == PLUS || outer == MINUS);
@@ -14058,7 +14058,7 @@ int
aarch64_branch_cost (bool speed_p, bool predictable_p)
{
/* When optimizing for speed, use the cost of unpredictable branches. */
- const struct cpu_branch_cost *branch_costs =
+ struct cpu_branch_cost *branch_costs =
aarch64_tune_params.branch_costs;
if (!speed_p || predictable_p)
@@ -14156,7 +14156,7 @@ aarch64_if_then_else_costs (rtx op0, rtx op1, rtx op2,
int *cost, bool speed)
rtx inner;
rtx comparator;
enum rtx_code cmpcode;
- const struct cpu_cost_table *extra_cost
+ struct cpu_cost_table *extra_cost
= aarch64_tune_params.insn_extra_cost;
if (COMPARISON_P (op0))
@@ -14396,7 +14396,7 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer
ATTRIBUTE_UNUSED,
int param ATTRIBUTE_UNUSED, int *cost, bool speed)
{
rtx op0, op1, op2;
- const struct cpu_cost_table *extra_cost
+ struct cpu_cost_table *extra_cost
= aarch64_tune_params.insn_extra_cost;
rtx_code code = GET_CODE (x);
scalar_int_mode int_mode;
@@ -16361,7 +16361,7 @@ class aarch64_vec_op_count
{
public:
aarch64_vec_op_count () = default;
- aarch64_vec_op_count (const aarch64_vec_issue_info *, unsigned int,
+ aarch64_vec_op_count (aarch64_vec_issue_info *, unsigned int,
unsigned int = 1);
unsigned int vec_flags () const { return m_vec_flags; }
@@ -16369,7 +16369,7 @@ public:
const aarch64_base_vec_issue_info *base_issue_info () const;
const aarch64_simd_vec_issue_info *simd_issue_info () const;
- const aarch64_sve_vec_issue_info *sve_issue_info () const;
+ aarch64_sve_vec_issue_info *sve_issue_info () const;
fractional_cost rename_cycles_per_iter () const;
fractional_cost min_nonpred_cycles_per_iter () const;
@@ -16398,7 +16398,7 @@ public:
private:
/* The issue information for the core. */
- const aarch64_vec_issue_info *m_issue_info = nullptr;
+ aarch64_vec_issue_info *m_issue_info = nullptr;
/* - If M_VEC_FLAGS is zero then this structure describes scalar code
- If M_VEC_FLAGS & VEC_ADVSIMD is nonzero then this structure describes
@@ -16418,7 +16418,7 @@ private:
};
aarch64_vec_op_count::
-aarch64_vec_op_count (const aarch64_vec_issue_info *issue_info,
+aarch64_vec_op_count (aarch64_vec_issue_info *issue_info,
unsigned int vec_flags, unsigned int vf_factor)
: m_issue_info (issue_info),
m_vec_flags (vec_flags),
@@ -16451,7 +16451,7 @@ aarch64_vec_op_count::simd_issue_info () const
/* If the structure describes SVE code and we have associated issue
information, return that issue information, otherwise return null. */
-const aarch64_sve_vec_issue_info *
+aarch64_sve_vec_issue_info *
aarch64_vec_op_count::sve_issue_info () const
{
if (m_vec_flags & VEC_ANY_SVE)
@@ -16699,7 +16699,7 @@ aarch64_vectorize_create_costs (vec_info *vinfo, bool
costing_for_scalar)
static const simd_vec_cost *
aarch64_simd_vec_costs (tree vectype)
{
- const cpu_vector_cost *costs = aarch64_tune_params.vec_costs;
+ cpu_vector_cost *costs = aarch64_tune_params.vec_costs;
if (vectype != NULL
&& aarch64_sve_mode_p (TYPE_MODE (vectype))
&& costs->sve != NULL)
@@ -16711,7 +16711,7 @@ aarch64_simd_vec_costs (tree vectype)
static const simd_vec_cost *
aarch64_simd_vec_costs_for_flags (unsigned int flags)
{
- const cpu_vector_cost *costs = aarch64_tune_params.vec_costs;
+ cpu_vector_cost *costs = aarch64_tune_params.vec_costs;
if ((flags & VEC_ANY_SVE) && costs->sve)
return costs->sve;
return costs->advsimd;
@@ -16808,7 +16808,7 @@ aarch64_builtin_vectorization_cost (enum
vect_cost_for_stmt type_of_cost,
int misalign ATTRIBUTE_UNUSED)
{
unsigned elements;
- const cpu_vector_cost *costs = aarch64_tune_params.vec_costs;
+ cpu_vector_cost *costs = aarch64_tune_params.vec_costs;
bool fp = false;
if (vectype != NULL)
@@ -17031,7 +17031,7 @@ aarch64_bool_compound_p (vec_info *vinfo, stmt_vec_info
stmt_info,
static unsigned int
aarch64_sve_in_loop_reduction_latency (vec_info *vinfo,
stmt_vec_info stmt_info,
- const sve_vec_cost *sve_costs)
+ sve_vec_cost *sve_costs)
{
switch (vect_reduc_type (vinfo, stmt_info))
{
@@ -17076,8 +17076,8 @@ static unsigned int
aarch64_in_loop_reduction_latency (vec_info *vinfo, stmt_vec_info stmt_info,
unsigned int vec_flags)
{
- const cpu_vector_cost *vec_costs = aarch64_tune_params.vec_costs;
- const sve_vec_cost *sve_costs = nullptr;
+ cpu_vector_cost *vec_costs = aarch64_tune_params.vec_costs;
+ sve_vec_cost *sve_costs = nullptr;
if (vec_flags & VEC_ANY_SVE)
sve_costs = aarch64_tune_params.vec_costs->sve;
@@ -17140,7 +17140,7 @@ aarch64_detect_vector_stmt_subtype (vec_info *vinfo,
vect_cost_for_stmt kind,
fractional_cost stmt_cost)
{
const simd_vec_cost *simd_costs = aarch64_simd_vec_costs (vectype);
- const sve_vec_cost *sve_costs = nullptr;
+ sve_vec_cost *sve_costs = nullptr;
if (aarch64_sve_mode_p (TYPE_MODE (vectype)))
sve_costs = aarch64_tune_params.vec_costs->sve;
@@ -17386,7 +17386,7 @@ aarch64_vector_costs::count_ops (unsigned int count,
vect_cost_for_stmt kind,
if (!base_issue)
return;
const aarch64_simd_vec_issue_info *simd_issue = ops->simd_issue_info ();
- const aarch64_sve_vec_issue_info *sve_issue = ops->sve_issue_info ();
+ aarch64_sve_vec_issue_info *sve_issue = ops->sve_issue_info ();
/* Calculate the minimum cycles per iteration imposed by a reduction
operation. */
@@ -17694,7 +17694,7 @@ aarch64_vector_costs::add_stmt_cost (int count,
vect_cost_for_stmt kind,
&& aarch64_sve_mode_p (TYPE_MODE (vectype))
&& vect_mem_access_type (stmt_info, node) == VMAT_GATHER_SCATTER)
{
- const sve_vec_cost *sve_costs = aarch64_tune_params.vec_costs->sve;
+ sve_vec_cost *sve_costs = aarch64_tune_params.vec_costs->sve;
if (sve_costs)
{
/* Test for VNx2 modes, which have 64-bit containers. */
diff --git a/gcc/config/aarch64/tuning_models/a64fx.h
b/gcc/config/aarch64/tuning_models/a64fx.h
index 2622cd80346..3f13f489349 100644
--- a/gcc/config/aarch64/tuning_models/a64fx.h
+++ b/gcc/config/aarch64/tuning_models/a64fx.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_addrcost_table a64fx_addrcost_table =
+static struct cpu_addrcost_table a64fx_addrcost_table =
{
{
1, /* hi */
@@ -40,7 +40,7 @@ static const struct cpu_addrcost_table a64fx_addrcost_table =
0, /* imm_offset */
};
-static const struct cpu_regmove_cost a64fx_regmove_cost =
+static struct cpu_regmove_cost a64fx_regmove_cost =
{
1, /* GP2GP */
/* Avoid the use of slow int<->fp moves for spilling by setting
@@ -50,7 +50,7 @@ static const struct cpu_regmove_cost a64fx_regmove_cost =
2 /* FP2FP */
};
-static const advsimd_vec_cost a64fx_advsimd_vector_cost =
+static advsimd_vec_cost a64fx_advsimd_vector_cost =
{
2, /* int_stmt_cost */
5, /* fp_stmt_cost */
@@ -74,7 +74,7 @@ static const advsimd_vec_cost a64fx_advsimd_vector_cost =
1 /* store_cost */
};
-static const sve_vec_cost a64fx_sve_vector_cost =
+static sve_vec_cost a64fx_sve_vector_cost =
{
{
2, /* int_stmt_cost */
@@ -109,7 +109,7 @@ static const sve_vec_cost a64fx_sve_vector_cost =
1 /* scatter_store_elt_cost */
};
-static const struct cpu_vector_cost a64fx_vector_cost =
+static struct cpu_vector_cost a64fx_vector_cost =
{
1, /* scalar_int_stmt_cost */
5, /* scalar_fp_stmt_cost */
@@ -122,7 +122,7 @@ static const struct cpu_vector_cost a64fx_vector_cost =
nullptr /* issue_info */
};
-static const cpu_prefetch_tune a64fx_prefetch_tune =
+static cpu_prefetch_tune a64fx_prefetch_tune =
{
8, /* num_slots */
64, /* l1_cache_size */
@@ -133,7 +133,7 @@ static const cpu_prefetch_tune a64fx_prefetch_tune =
-1 /* default_opt_level */
};
-static const struct tune_params a64fx_tunings =
+static struct tune_params a64fx_tunings =
{
&a64fx_extra_costs,
&a64fx_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/ampere1.h
b/gcc/config/aarch64/tuning_models/ampere1.h
index f033016d010..10c53d85f1d 100644
--- a/gcc/config/aarch64/tuning_models/ampere1.h
+++ b/gcc/config/aarch64/tuning_models/ampere1.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const advsimd_vec_cost ampere1_advsimd_vector_cost =
+static advsimd_vec_cost ampere1_advsimd_vector_cost =
{
1, /* int_stmt_cost */
3, /* fp_stmt_cost */
@@ -47,7 +47,7 @@ static const advsimd_vec_cost ampere1_advsimd_vector_cost =
};
/* Ampere-1 costs for vector insn classes. */
-static const struct cpu_vector_cost ampere1_vector_cost =
+static struct cpu_vector_cost ampere1_vector_cost =
{
1, /* scalar_int_stmt_cost */
3, /* scalar_fp_stmt_cost */
@@ -60,7 +60,7 @@ static const struct cpu_vector_cost ampere1_vector_cost =
nullptr /* issue_info */
};
-static const cpu_prefetch_tune ampere1_prefetch_tune =
+static cpu_prefetch_tune ampere1_prefetch_tune =
{
0, /* num_slots */
64, /* l1_cache_size */
@@ -71,7 +71,7 @@ static const cpu_prefetch_tune ampere1_prefetch_tune =
-1 /* default_opt_level */
};
-static const struct tune_params ampere1_tunings =
+static struct tune_params ampere1_tunings =
{
&ere1_extra_costs,
&generic_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/ampere1a.h
b/gcc/config/aarch64/tuning_models/ampere1a.h
index 41481a7f077..720b0468f2c 100644
--- a/gcc/config/aarch64/tuning_models/ampere1a.h
+++ b/gcc/config/aarch64/tuning_models/ampere1a.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct tune_params ampere1a_tunings =
+static struct tune_params ampere1a_tunings =
{
&ere1a_extra_costs,
&generic_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/ampere1b.h
b/gcc/config/aarch64/tuning_models/ampere1b.h
index 2ad6003d65c..735a9755004 100644
--- a/gcc/config/aarch64/tuning_models/ampere1b.h
+++ b/gcc/config/aarch64/tuning_models/ampere1b.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const cpu_prefetch_tune ampere1b_prefetch_tune =
+static cpu_prefetch_tune ampere1b_prefetch_tune =
{
48, /* num_slots */
64, /* l1_cache_size */
@@ -33,7 +33,7 @@ static const cpu_prefetch_tune ampere1b_prefetch_tune =
-1 /* default_opt_level */
};
-static const advsimd_vec_cost ampere1b_advsimd_vector_cost =
+static advsimd_vec_cost ampere1b_advsimd_vector_cost =
{
1, /* int_stmt_cost */
3, /* fp_stmt_cost */
@@ -58,7 +58,7 @@ static const advsimd_vec_cost ampere1b_advsimd_vector_cost =
};
/* Ampere-1B costs for vector insn classes. */
-static const struct cpu_vector_cost ampere1b_vector_cost =
+static struct cpu_vector_cost ampere1b_vector_cost =
{
1, /* scalar_int_stmt_cost */
3, /* scalar_fp_stmt_cost */
@@ -71,7 +71,7 @@ static const struct cpu_vector_cost ampere1b_vector_cost =
nullptr /* issue_info */
};
-static const struct tune_params ampere1b_tunings =
+static struct tune_params ampere1b_tunings =
{
&ere1b_extra_costs,
&generic_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/cortexa35.h
b/gcc/config/aarch64/tuning_models/cortexa35.h
index 56168c8ebc6..108ed4d4ab4 100644
--- a/gcc/config/aarch64/tuning_models/cortexa35.h
+++ b/gcc/config/aarch64/tuning_models/cortexa35.h
@@ -23,7 +23,7 @@
#include "generic.h"
#include "cortexa53.h"
-static const struct tune_params cortexa35_tunings =
+static struct tune_params cortexa35_tunings =
{
&cortexa53_extra_costs,
&generic_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/cortexa53.h
b/gcc/config/aarch64/tuning_models/cortexa53.h
index 83daae4d38c..b7e1586ff12 100644
--- a/gcc/config/aarch64/tuning_models/cortexa53.h
+++ b/gcc/config/aarch64/tuning_models/cortexa53.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_regmove_cost cortexa53_regmove_cost =
+static struct cpu_regmove_cost cortexa53_regmove_cost =
{
1, /* GP2GP */
/* Avoid the use of slow int<->fp moves for spilling by setting
@@ -32,7 +32,7 @@ static const struct cpu_regmove_cost cortexa53_regmove_cost =
2 /* FP2FP */
};
-static const struct tune_params cortexa53_tunings =
+static struct tune_params cortexa53_tunings =
{
&cortexa53_extra_costs,
&generic_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/cortexa57.h
b/gcc/config/aarch64/tuning_models/cortexa57.h
index 8da7fa9d80d..29cae0f5431 100644
--- a/gcc/config/aarch64/tuning_models/cortexa57.h
+++ b/gcc/config/aarch64/tuning_models/cortexa57.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_regmove_cost cortexa57_regmove_cost =
+static struct cpu_regmove_cost cortexa57_regmove_cost =
{
1, /* GP2GP */
/* Avoid the use of slow int<->fp moves for spilling by setting
@@ -32,7 +32,7 @@ static const struct cpu_regmove_cost cortexa57_regmove_cost =
2 /* FP2FP */
};
-static const advsimd_vec_cost cortexa57_advsimd_vector_cost =
+static advsimd_vec_cost cortexa57_advsimd_vector_cost =
{
2, /* int_stmt_cost */
2, /* fp_stmt_cost */
@@ -57,7 +57,7 @@ static const advsimd_vec_cost cortexa57_advsimd_vector_cost =
};
/* Cortex-A57 costs for vector insn classes. */
-static const struct cpu_vector_cost cortexa57_vector_cost =
+static struct cpu_vector_cost cortexa57_vector_cost =
{
1, /* scalar_int_stmt_cost */
1, /* scalar_fp_stmt_cost */
@@ -70,7 +70,7 @@ static const struct cpu_vector_cost cortexa57_vector_cost =
nullptr /* issue_info */
};
-static const struct tune_params cortexa57_tunings =
+static struct tune_params cortexa57_tunings =
{
&cortexa57_extra_costs,
&generic_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/cortexa72.h
b/gcc/config/aarch64/tuning_models/cortexa72.h
index f9a330f4a18..bdf57c2f536 100644
--- a/gcc/config/aarch64/tuning_models/cortexa72.h
+++ b/gcc/config/aarch64/tuning_models/cortexa72.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct tune_params cortexa72_tunings =
+static struct tune_params cortexa72_tunings =
{
&cortexa57_extra_costs,
&generic_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/cortexa73.h
b/gcc/config/aarch64/tuning_models/cortexa73.h
index 038fd0896b9..63d2c2d7bb8 100644
--- a/gcc/config/aarch64/tuning_models/cortexa73.h
+++ b/gcc/config/aarch64/tuning_models/cortexa73.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct tune_params cortexa73_tunings =
+static struct tune_params cortexa73_tunings =
{
&cortexa57_extra_costs,
&generic_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/cortexx925.h
b/gcc/config/aarch64/tuning_models/cortexx925.h
index 7d0162eae54..bb133b63e31 100644
--- a/gcc/config/aarch64/tuning_models/cortexx925.h
+++ b/gcc/config/aarch64/tuning_models/cortexx925.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_regmove_cost cortexx925_regmove_cost =
+static struct cpu_regmove_cost cortexx925_regmove_cost =
{
3, /* GP2GP */
/* Spilling to int<->fp instead of memory is recommended so set
@@ -32,7 +32,7 @@ static const struct cpu_regmove_cost cortexx925_regmove_cost =
4 /* FP2FP */
};
-static const advsimd_vec_cost cortexx925_advsimd_vector_cost =
+static advsimd_vec_cost cortexx925_advsimd_vector_cost =
{
2, /* int_stmt_cost */
2, /* fp_stmt_cost */
@@ -63,7 +63,7 @@ static const advsimd_vec_cost cortexx925_advsimd_vector_cost =
1 /* store_cost */
};
-static const sve_vec_cost cortexx925_sve_vector_cost =
+static sve_vec_cost cortexx925_sve_vector_cost =
{
{
2, /* int_stmt_cost */
@@ -122,7 +122,7 @@ static const sve_vec_cost cortexx925_sve_vector_cost =
1 /* scatter_store_elt_cost */
};
-static const aarch64_scalar_vec_issue_info cortexx925_scalar_issue_info =
+static aarch64_scalar_vec_issue_info cortexx925_scalar_issue_info =
{
4, /* loads_stores_per_cycle */
2, /* stores_per_cycle */
@@ -131,7 +131,7 @@ static const aarch64_scalar_vec_issue_info
cortexx925_scalar_issue_info =
1 /* fp_simd_store_general_ops */
};
-static const aarch64_advsimd_vec_issue_info cortexx925_advsimd_issue_info =
+static aarch64_advsimd_vec_issue_info cortexx925_advsimd_issue_info =
{
{
4, /* loads_stores_per_cycle */
@@ -145,7 +145,7 @@ static const aarch64_advsimd_vec_issue_info
cortexx925_advsimd_issue_info =
3 /* ld4_st4_general_ops */
};
-static const aarch64_sve_vec_issue_info cortexx925_sve_issue_info =
+static aarch64_sve_vec_issue_info cortexx925_sve_issue_info =
{
{
{
@@ -167,7 +167,7 @@ static const aarch64_sve_vec_issue_info
cortexx925_sve_issue_info =
1 /* gather_scatter_pair_pred_ops */
};
-static const aarch64_vec_issue_info cortexx925_vec_issue_info =
+static aarch64_vec_issue_info cortexx925_vec_issue_info =
{
&cortexx925_scalar_issue_info,
&cortexx925_advsimd_issue_info,
@@ -175,7 +175,7 @@ static const aarch64_vec_issue_info
cortexx925_vec_issue_info =
};
/* Cortexx925 costs for vector insn classes. */
-static const struct cpu_vector_cost cortexx925_vector_cost =
+static struct cpu_vector_cost cortexx925_vector_cost =
{
1, /* scalar_int_stmt_cost */
2, /* scalar_fp_stmt_cost */
@@ -188,7 +188,7 @@ static const struct cpu_vector_cost cortexx925_vector_cost =
&cortexx925_vec_issue_info /* issue_info */
};
-static const struct tune_params cortexx925_tunings =
+static struct tune_params cortexx925_tunings =
{
&cortexa76_extra_costs,
&generic_armv9_a_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/emag.h
b/gcc/config/aarch64/tuning_models/emag.h
index 264a2810299..304cfc0901e 100644
--- a/gcc/config/aarch64/tuning_models/emag.h
+++ b/gcc/config/aarch64/tuning_models/emag.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct tune_params emag_tunings =
+static struct tune_params emag_tunings =
{
&xgene1_extra_costs,
&xgene1_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/exynosm1.h
b/gcc/config/aarch64/tuning_models/exynosm1.h
index 71876df7785..c947d002981 100644
--- a/gcc/config/aarch64/tuning_models/exynosm1.h
+++ b/gcc/config/aarch64/tuning_models/exynosm1.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_addrcost_table exynosm1_addrcost_table =
+static struct cpu_addrcost_table exynosm1_addrcost_table =
{
{
0, /* hi */
@@ -40,7 +40,7 @@ static const struct cpu_addrcost_table
exynosm1_addrcost_table =
0, /* imm_offset */
};
-static const struct cpu_regmove_cost exynosm1_regmove_cost =
+static struct cpu_regmove_cost exynosm1_regmove_cost =
{
1, /* GP2GP */
/* Avoid the use of slow int<->fp moves for spilling by setting
@@ -50,7 +50,7 @@ static const struct cpu_regmove_cost exynosm1_regmove_cost =
1 /* FP2FP */
};
-static const advsimd_vec_cost exynosm1_advsimd_vector_cost =
+static advsimd_vec_cost exynosm1_advsimd_vector_cost =
{
3, /* int_stmt_cost */
3, /* fp_stmt_cost */
@@ -74,7 +74,7 @@ static const advsimd_vec_cost exynosm1_advsimd_vector_cost =
1 /* store_cost */
};
-static const struct cpu_vector_cost exynosm1_vector_cost =
+static struct cpu_vector_cost exynosm1_vector_cost =
{
1, /* scalar_int_stmt_cost */
1, /* scalar_fp_stmt_cost */
@@ -88,14 +88,14 @@ static const struct cpu_vector_cost exynosm1_vector_cost =
};
/* Approximation modes for Exynos M1. */
-static const cpu_approx_modes exynosm1_approx_modes =
+static cpu_approx_modes exynosm1_approx_modes =
{
AARCH64_APPROX_NONE, /* division */
AARCH64_APPROX_ALL, /* sqrt */
AARCH64_APPROX_ALL /* recip_sqrt */
};
-static const cpu_prefetch_tune exynosm1_prefetch_tune =
+static cpu_prefetch_tune exynosm1_prefetch_tune =
{
0, /* num_slots */
-1, /* l1_cache_size */
@@ -106,7 +106,7 @@ static const cpu_prefetch_tune exynosm1_prefetch_tune =
-1 /* default_opt_level */
};
-static const struct tune_params exynosm1_tunings =
+static struct tune_params exynosm1_tunings =
{
&exynosm1_extra_costs,
&exynosm1_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/fujitsu_monaka.h
b/gcc/config/aarch64/tuning_models/fujitsu_monaka.h
index 5dc40243fe3..306e21a06d2 100644
--- a/gcc/config/aarch64/tuning_models/fujitsu_monaka.h
+++ b/gcc/config/aarch64/tuning_models/fujitsu_monaka.h
@@ -25,7 +25,7 @@
/* Tuning parameters for FUJITSU-MONAKA processor. It is copied from the
generic one except for the vector width for now. */
-static const struct tune_params fujitsu_monaka_tunings =
+static struct tune_params fujitsu_monaka_tunings =
{
&cortexa76_extra_costs,
&generic_armv9_a_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/generic.h
b/gcc/config/aarch64/tuning_models/generic.h
index a822c055fe9..daefcf81726 100644
--- a/gcc/config/aarch64/tuning_models/generic.h
+++ b/gcc/config/aarch64/tuning_models/generic.h
@@ -21,7 +21,7 @@
#ifndef GCC_AARCH64_H_GENERIC
#define GCC_AARCH64_H_GENERIC
-static const struct cpu_addrcost_table generic_addrcost_table =
+static struct cpu_addrcost_table generic_addrcost_table =
{
{
1, /* hi */
@@ -39,7 +39,7 @@ static const struct cpu_addrcost_table generic_addrcost_table
=
0 /* imm_offset */
};
-static const struct cpu_regmove_cost generic_regmove_cost =
+static struct cpu_regmove_cost generic_regmove_cost =
{
1, /* GP2GP */
/* Avoid the use of slow int<->fp moves for spilling by setting
@@ -50,7 +50,7 @@ static const struct cpu_regmove_cost generic_regmove_cost =
};
/* Generic costs for Advanced SIMD vector operations. */
-static const advsimd_vec_cost generic_advsimd_vector_cost =
+static advsimd_vec_cost generic_advsimd_vector_cost =
{
1, /* int_stmt_cost */
1, /* fp_stmt_cost */
@@ -75,7 +75,7 @@ static const advsimd_vec_cost generic_advsimd_vector_cost =
};
/* Generic costs for SVE vector operations. */
-static const sve_vec_cost generic_sve_vector_cost =
+static sve_vec_cost generic_sve_vector_cost =
{
{
1, /* int_stmt_cost */
@@ -111,7 +111,7 @@ static const sve_vec_cost generic_sve_vector_cost =
};
/* Generic costs for vector insn classes. */
-static const struct cpu_vector_cost generic_vector_cost =
+static struct cpu_vector_cost generic_vector_cost =
{
1, /* scalar_int_stmt_cost */
1, /* scalar_fp_stmt_cost */
@@ -125,14 +125,14 @@ static const struct cpu_vector_cost generic_vector_cost =
};
/* Generic costs for branch instructions. */
-static const struct cpu_branch_cost generic_branch_cost =
+static struct cpu_branch_cost generic_branch_cost =
{
1, /* Predictable. */
3 /* Unpredictable. */
};
/* Generic approximation modes. */
-static const cpu_approx_modes generic_approx_modes =
+static cpu_approx_modes generic_approx_modes =
{
AARCH64_APPROX_NONE, /* division */
AARCH64_APPROX_NONE, /* sqrt */
@@ -140,7 +140,7 @@ static const cpu_approx_modes generic_approx_modes =
};
/* Generic prefetch settings (which disable prefetch). */
-static const cpu_prefetch_tune generic_prefetch_tune =
+static cpu_prefetch_tune generic_prefetch_tune =
{
0, /* num_slots */
-1, /* l1_cache_size */
@@ -151,7 +151,7 @@ static const cpu_prefetch_tune generic_prefetch_tune =
-1 /* default_opt_level */
};
-static const struct tune_params generic_tunings =
+static struct tune_params generic_tunings =
{
&cortexa57_extra_costs,
&generic_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/generic_armv8_a.h
b/gcc/config/aarch64/tuning_models/generic_armv8_a.h
index 35de3f03296..e70eba3a404 100644
--- a/gcc/config/aarch64/tuning_models/generic_armv8_a.h
+++ b/gcc/config/aarch64/tuning_models/generic_armv8_a.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_addrcost_table generic_armv8_a_addrcost_table =
+static struct cpu_addrcost_table generic_armv8_a_addrcost_table =
{
{
1, /* hi */
@@ -40,7 +40,7 @@ static const struct cpu_addrcost_table
generic_armv8_a_addrcost_table =
0 /* imm_offset */
};
-static const struct cpu_regmove_cost generic_armv8_a_regmove_cost =
+static struct cpu_regmove_cost generic_armv8_a_regmove_cost =
{
1, /* GP2GP */
/* Avoid the use of slow int<->fp moves for spilling by setting
@@ -51,7 +51,7 @@ static const struct cpu_regmove_cost
generic_armv8_a_regmove_cost =
};
/* Generic costs for Advanced SIMD vector operations. */
-static const advsimd_vec_cost generic_armv8_a_advsimd_vector_cost =
+static advsimd_vec_cost generic_armv8_a_advsimd_vector_cost =
{
1, /* int_stmt_cost */
1, /* fp_stmt_cost */
@@ -76,7 +76,7 @@ static const advsimd_vec_cost
generic_armv8_a_advsimd_vector_cost =
};
/* Generic costs for SVE vector operations. */
-static const sve_vec_cost generic_armv8_a_sve_vector_cost =
+static sve_vec_cost generic_armv8_a_sve_vector_cost =
{
{
1, /* int_stmt_cost */
@@ -112,7 +112,7 @@ static const sve_vec_cost generic_armv8_a_sve_vector_cost =
};
/* Generic costs for vector insn classes. */
-static const struct cpu_vector_cost generic_armv8_a_vector_cost =
+static struct cpu_vector_cost generic_armv8_a_vector_cost =
{
1, /* scalar_int_stmt_cost */
1, /* scalar_fp_stmt_cost */
@@ -126,14 +126,14 @@ static const struct cpu_vector_cost
generic_armv8_a_vector_cost =
};
/* Generic costs for branch instructions. */
-static const struct cpu_branch_cost generic_armv8_a_branch_cost =
+static struct cpu_branch_cost generic_armv8_a_branch_cost =
{
1, /* Predictable. */
3 /* Unpredictable. */
};
/* Generic approximation modes. */
-static const cpu_approx_modes generic_armv8_a_approx_modes =
+static cpu_approx_modes generic_armv8_a_approx_modes =
{
AARCH64_APPROX_NONE, /* division */
AARCH64_APPROX_NONE, /* sqrt */
@@ -141,7 +141,7 @@ static const cpu_approx_modes generic_armv8_a_approx_modes =
};
/* Generic prefetch settings (which disable prefetch). */
-static const cpu_prefetch_tune generic_armv8_a_prefetch_tune =
+static cpu_prefetch_tune generic_armv8_a_prefetch_tune =
{
0, /* num_slots */
-1, /* l1_cache_size */
@@ -152,7 +152,7 @@ static const cpu_prefetch_tune
generic_armv8_a_prefetch_tune =
-1 /* default_opt_level */
};
-static const struct tune_params generic_armv8_a_tunings =
+static struct tune_params generic_armv8_a_tunings =
{
&cortexa76_extra_costs,
&generic_armv8_a_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/generic_armv9_a.h
b/gcc/config/aarch64/tuning_models/generic_armv9_a.h
index f76a2506f38..9c1a8697b38 100644
--- a/gcc/config/aarch64/tuning_models/generic_armv9_a.h
+++ b/gcc/config/aarch64/tuning_models/generic_armv9_a.h
@@ -23,7 +23,7 @@
#include "generic.h"
#include "generic_armv8_a.h"
-static const struct cpu_addrcost_table generic_armv9_a_addrcost_table =
+static struct cpu_addrcost_table generic_armv9_a_addrcost_table =
{
{
1, /* hi */
@@ -41,7 +41,7 @@ static const struct cpu_addrcost_table
generic_armv9_a_addrcost_table =
0 /* imm_offset */
};
-static const struct cpu_regmove_cost generic_armv9_a_regmove_cost =
+static struct cpu_regmove_cost generic_armv9_a_regmove_cost =
{
1, /* GP2GP */
/* Spilling to int<->fp instead of memory is recommended so set
@@ -51,7 +51,7 @@ static const struct cpu_regmove_cost
generic_armv9_a_regmove_cost =
2 /* FP2FP */
};
-static const advsimd_vec_cost generic_armv9_a_advsimd_vector_cost =
+static advsimd_vec_cost generic_armv9_a_advsimd_vector_cost =
{
2, /* int_stmt_cost */
2, /* fp_stmt_cost */
@@ -82,7 +82,7 @@ static const advsimd_vec_cost
generic_armv9_a_advsimd_vector_cost =
1 /* store_cost */
};
-static const sve_vec_cost generic_armv9_a_sve_vector_cost =
+static sve_vec_cost generic_armv9_a_sve_vector_cost =
{
{
2, /* int_stmt_cost */
@@ -141,7 +141,7 @@ static const sve_vec_cost generic_armv9_a_sve_vector_cost =
3 /* scatter_store_elt_cost */
};
-static const aarch64_scalar_vec_issue_info generic_armv9_a_scalar_issue_info =
+static aarch64_scalar_vec_issue_info generic_armv9_a_scalar_issue_info =
{
3, /* loads_stores_per_cycle */
2, /* stores_per_cycle */
@@ -150,7 +150,7 @@ static const aarch64_scalar_vec_issue_info
generic_armv9_a_scalar_issue_info =
1 /* fp_simd_store_general_ops */
};
-static const aarch64_advsimd_vec_issue_info generic_armv9_a_advsimd_issue_info
=
+static aarch64_advsimd_vec_issue_info generic_armv9_a_advsimd_issue_info =
{
{
3, /* loads_stores_per_cycle */
@@ -164,7 +164,7 @@ static const aarch64_advsimd_vec_issue_info
generic_armv9_a_advsimd_issue_info =
3 /* ld4_st4_general_ops */
};
-static const aarch64_sve_vec_issue_info generic_armv9_a_sve_issue_info =
+static aarch64_sve_vec_issue_info generic_armv9_a_sve_issue_info =
{
{
{
@@ -186,7 +186,7 @@ static const aarch64_sve_vec_issue_info
generic_armv9_a_sve_issue_info =
1 /* gather_scatter_pair_pred_ops */
};
-static const aarch64_vec_issue_info generic_armv9_a_vec_issue_info =
+static aarch64_vec_issue_info generic_armv9_a_vec_issue_info =
{
&generic_armv9_a_scalar_issue_info,
&generic_armv9_a_advsimd_issue_info,
@@ -194,7 +194,7 @@ static const aarch64_vec_issue_info
generic_armv9_a_vec_issue_info =
};
/* Generic_armv9_a costs for vector insn classes. */
-static const struct cpu_vector_cost generic_armv9_a_vector_cost =
+static struct cpu_vector_cost generic_armv9_a_vector_cost =
{
1, /* scalar_int_stmt_cost */
2, /* scalar_fp_stmt_cost */
@@ -208,7 +208,7 @@ static const struct cpu_vector_cost
generic_armv9_a_vector_cost =
};
/* Generic prefetch settings (which disable prefetch). */
-static const cpu_prefetch_tune generic_armv9a_prefetch_tune =
+static cpu_prefetch_tune generic_armv9a_prefetch_tune =
{
0, /* num_slots */
-1, /* l1_cache_size */
@@ -219,7 +219,7 @@ static const cpu_prefetch_tune generic_armv9a_prefetch_tune
=
-1 /* default_opt_level */
};
-static const struct tune_params generic_armv9_a_tunings =
+static struct tune_params generic_armv9_a_tunings =
{
&cortexa76_extra_costs,
&generic_armv9_a_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/neoverse512tvb.h
b/gcc/config/aarch64/tuning_models/neoverse512tvb.h
index 964b4ac284a..9c69e58a906 100644
--- a/gcc/config/aarch64/tuning_models/neoverse512tvb.h
+++ b/gcc/config/aarch64/tuning_models/neoverse512tvb.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const sve_vec_cost neoverse512tvb_sve_vector_cost =
+static sve_vec_cost neoverse512tvb_sve_vector_cost =
{
{
2, /* int_stmt_cost */
@@ -84,7 +84,7 @@ static const sve_vec_cost neoverse512tvb_sve_vector_cost =
3 /* scatter_store_elt_cost */
};
-static const aarch64_sve_vec_issue_info neoverse512tvb_sve_issue_info =
+static aarch64_sve_vec_issue_info neoverse512tvb_sve_issue_info =
{
{
{
@@ -106,14 +106,14 @@ static const aarch64_sve_vec_issue_info
neoverse512tvb_sve_issue_info =
1 /* gather_scatter_pair_pred_ops */
};
-static const aarch64_vec_issue_info neoverse512tvb_vec_issue_info =
+static aarch64_vec_issue_info neoverse512tvb_vec_issue_info =
{
&neoversev1_scalar_issue_info,
&neoversev1_advsimd_issue_info,
&neoverse512tvb_sve_issue_info
};
-static const struct cpu_vector_cost neoverse512tvb_vector_cost =
+static struct cpu_vector_cost neoverse512tvb_vector_cost =
{
1, /* scalar_int_stmt_cost */
2, /* scalar_fp_stmt_cost */
@@ -126,7 +126,7 @@ static const struct cpu_vector_cost
neoverse512tvb_vector_cost =
&neoverse512tvb_vec_issue_info /* issue_info */
};
-static const struct tune_params neoverse512tvb_tunings =
+static struct tune_params neoverse512tvb_tunings =
{
&cortexa76_extra_costs,
&neoversev1_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/neoversen1.h
b/gcc/config/aarch64/tuning_models/neoversen1.h
index 9dc37bd7fd6..d70700cb691 100644
--- a/gcc/config/aarch64/tuning_models/neoversen1.h
+++ b/gcc/config/aarch64/tuning_models/neoversen1.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct tune_params neoversen1_tunings =
+static struct tune_params neoversen1_tunings =
{
&cortexa76_extra_costs,
&generic_armv8_a_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/neoversen2.h
b/gcc/config/aarch64/tuning_models/neoversen2.h
index 9fbc059ea12..8bec9777c95 100644
--- a/gcc/config/aarch64/tuning_models/neoversen2.h
+++ b/gcc/config/aarch64/tuning_models/neoversen2.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_regmove_cost neoversen2_regmove_cost =
+static struct cpu_regmove_cost neoversen2_regmove_cost =
{
1, /* GP2GP */
/* Spilling to int<->fp instead of memory is recommended so set
@@ -32,7 +32,7 @@ static const struct cpu_regmove_cost neoversen2_regmove_cost =
2 /* FP2FP */
};
-static const advsimd_vec_cost neoversen2_advsimd_vector_cost =
+static advsimd_vec_cost neoversen2_advsimd_vector_cost =
{
2, /* int_stmt_cost */
2, /* fp_stmt_cost */
@@ -63,7 +63,7 @@ static const advsimd_vec_cost neoversen2_advsimd_vector_cost =
1 /* store_cost */
};
-static const sve_vec_cost neoversen2_sve_vector_cost =
+static sve_vec_cost neoversen2_sve_vector_cost =
{
{
2, /* int_stmt_cost */
@@ -122,7 +122,7 @@ static const sve_vec_cost neoversen2_sve_vector_cost =
3 /* scatter_store_elt_cost */
};
-static const aarch64_scalar_vec_issue_info neoversen2_scalar_issue_info =
+static aarch64_scalar_vec_issue_info neoversen2_scalar_issue_info =
{
3, /* loads_stores_per_cycle */
2, /* stores_per_cycle */
@@ -131,7 +131,7 @@ static const aarch64_scalar_vec_issue_info
neoversen2_scalar_issue_info =
1 /* fp_simd_store_general_ops */
};
-static const aarch64_advsimd_vec_issue_info neoversen2_advsimd_issue_info =
+static aarch64_advsimd_vec_issue_info neoversen2_advsimd_issue_info =
{
{
3, /* loads_stores_per_cycle */
@@ -145,7 +145,7 @@ static const aarch64_advsimd_vec_issue_info
neoversen2_advsimd_issue_info =
3 /* ld4_st4_general_ops */
};
-static const aarch64_sve_vec_issue_info neoversen2_sve_issue_info =
+static aarch64_sve_vec_issue_info neoversen2_sve_issue_info =
{
{
{
@@ -167,7 +167,7 @@ static const aarch64_sve_vec_issue_info
neoversen2_sve_issue_info =
1 /* gather_scatter_pair_pred_ops */
};
-static const aarch64_vec_issue_info neoversen2_vec_issue_info =
+static aarch64_vec_issue_info neoversen2_vec_issue_info =
{
&neoversen2_scalar_issue_info,
&neoversen2_advsimd_issue_info,
@@ -175,7 +175,7 @@ static const aarch64_vec_issue_info
neoversen2_vec_issue_info =
};
/* Neoversen2 costs for vector insn classes. */
-static const struct cpu_vector_cost neoversen2_vector_cost =
+static struct cpu_vector_cost neoversen2_vector_cost =
{
1, /* scalar_int_stmt_cost */
2, /* scalar_fp_stmt_cost */
@@ -188,7 +188,7 @@ static const struct cpu_vector_cost neoversen2_vector_cost =
&neoversen2_vec_issue_info /* issue_info */
};
-static const struct tune_params neoversen2_tunings =
+static struct tune_params neoversen2_tunings =
{
&cortexa76_extra_costs,
&generic_armv9_a_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/neoversen3.h
b/gcc/config/aarch64/tuning_models/neoversen3.h
index 78177e78e07..03a1d24fb0d 100644
--- a/gcc/config/aarch64/tuning_models/neoversen3.h
+++ b/gcc/config/aarch64/tuning_models/neoversen3.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_regmove_cost neoversen3_regmove_cost =
+static struct cpu_regmove_cost neoversen3_regmove_cost =
{
3, /* GP2GP */
/* Spilling to int<->fp instead of memory is recommended so set
@@ -32,7 +32,7 @@ static const struct cpu_regmove_cost neoversen3_regmove_cost =
4 /* FP2FP */
};
-static const advsimd_vec_cost neoversen3_advsimd_vector_cost =
+static advsimd_vec_cost neoversen3_advsimd_vector_cost =
{
2, /* int_stmt_cost */
2, /* fp_stmt_cost */
@@ -63,7 +63,7 @@ static const advsimd_vec_cost neoversen3_advsimd_vector_cost =
1 /* store_cost */
};
-static const sve_vec_cost neoversen3_sve_vector_cost =
+static sve_vec_cost neoversen3_sve_vector_cost =
{
{
2, /* int_stmt_cost */
@@ -122,7 +122,7 @@ static const sve_vec_cost neoversen3_sve_vector_cost =
1 /* scatter_store_elt_cost */
};
-static const aarch64_scalar_vec_issue_info neoversen3_scalar_issue_info =
+static aarch64_scalar_vec_issue_info neoversen3_scalar_issue_info =
{
3, /* loads_stores_per_cycle */
2, /* stores_per_cycle */
@@ -131,7 +131,7 @@ static const aarch64_scalar_vec_issue_info
neoversen3_scalar_issue_info =
1 /* fp_simd_store_general_ops */
};
-static const aarch64_advsimd_vec_issue_info neoversen3_advsimd_issue_info =
+static aarch64_advsimd_vec_issue_info neoversen3_advsimd_issue_info =
{
{
3, /* loads_stores_per_cycle */
@@ -145,7 +145,7 @@ static const aarch64_advsimd_vec_issue_info
neoversen3_advsimd_issue_info =
3 /* ld4_st4_general_ops */
};
-static const aarch64_sve_vec_issue_info neoversen3_sve_issue_info =
+static aarch64_sve_vec_issue_info neoversen3_sve_issue_info =
{
{
{
@@ -167,7 +167,7 @@ static const aarch64_sve_vec_issue_info
neoversen3_sve_issue_info =
1 /* gather_scatter_pair_pred_ops */
};
-static const aarch64_vec_issue_info neoversen3_vec_issue_info =
+static aarch64_vec_issue_info neoversen3_vec_issue_info =
{
&neoversen3_scalar_issue_info,
&neoversen3_advsimd_issue_info,
@@ -175,7 +175,7 @@ static const aarch64_vec_issue_info
neoversen3_vec_issue_info =
};
/* Neoversen3 costs for vector insn classes. */
-static const struct cpu_vector_cost neoversen3_vector_cost =
+static struct cpu_vector_cost neoversen3_vector_cost =
{
1, /* scalar_int_stmt_cost */
2, /* scalar_fp_stmt_cost */
@@ -188,7 +188,7 @@ static const struct cpu_vector_cost neoversen3_vector_cost =
&neoversen3_vec_issue_info /* issue_info */
};
-static const struct tune_params neoversen3_tunings =
+static struct tune_params neoversen3_tunings =
{
&cortexa76_extra_costs,
&generic_armv9_a_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/neoversev1.h
b/gcc/config/aarch64/tuning_models/neoversev1.h
index f1ec7dcdda7..4e3c5fc84e3 100644
--- a/gcc/config/aarch64/tuning_models/neoversev1.h
+++ b/gcc/config/aarch64/tuning_models/neoversev1.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_addrcost_table neoversev1_addrcost_table =
+static struct cpu_addrcost_table neoversev1_addrcost_table =
{
{
1, /* hi */
@@ -40,7 +40,7 @@ static const struct cpu_addrcost_table
neoversev1_addrcost_table =
0 /* imm_offset */
};
-static const struct cpu_regmove_cost neoversev1_regmove_cost =
+static struct cpu_regmove_cost neoversev1_regmove_cost =
{
1, /* GP2GP */
/* Spilling to int<->fp instead of memory is recommended so set
@@ -50,7 +50,7 @@ static const struct cpu_regmove_cost neoversev1_regmove_cost =
2 /* FP2FP */
};
-static const advsimd_vec_cost neoversev1_advsimd_vector_cost =
+static advsimd_vec_cost neoversev1_advsimd_vector_cost =
{
2, /* int_stmt_cost */
2, /* fp_stmt_cost */
@@ -81,7 +81,7 @@ static const advsimd_vec_cost neoversev1_advsimd_vector_cost =
1 /* store_cost */
};
-static const sve_vec_cost neoversev1_sve_vector_cost =
+static sve_vec_cost neoversev1_sve_vector_cost =
{
{
2, /* int_stmt_cost */
@@ -131,7 +131,7 @@ static const sve_vec_cost neoversev1_sve_vector_cost =
3 /* scatter_store_elt_cost */
};
-static const aarch64_scalar_vec_issue_info neoversev1_scalar_issue_info =
+static aarch64_scalar_vec_issue_info neoversev1_scalar_issue_info =
{
3, /* loads_stores_per_cycle */
2, /* stores_per_cycle */
@@ -140,7 +140,7 @@ static const aarch64_scalar_vec_issue_info
neoversev1_scalar_issue_info =
1 /* fp_simd_store_general_ops */
};
-static const aarch64_advsimd_vec_issue_info neoversev1_advsimd_issue_info =
+static aarch64_advsimd_vec_issue_info neoversev1_advsimd_issue_info =
{
{
3, /* loads_stores_per_cycle */
@@ -154,7 +154,7 @@ static const aarch64_advsimd_vec_issue_info
neoversev1_advsimd_issue_info =
3 /* ld4_st4_general_ops */
};
-static const aarch64_sve_vec_issue_info neoversev1_sve_issue_info =
+static aarch64_sve_vec_issue_info neoversev1_sve_issue_info =
{
{
{
@@ -176,7 +176,7 @@ static const aarch64_sve_vec_issue_info
neoversev1_sve_issue_info =
1 /* gather_scatter_pair_pred_ops */
};
-static const aarch64_vec_issue_info neoversev1_vec_issue_info =
+static aarch64_vec_issue_info neoversev1_vec_issue_info =
{
&neoversev1_scalar_issue_info,
&neoversev1_advsimd_issue_info,
@@ -184,7 +184,7 @@ static const aarch64_vec_issue_info
neoversev1_vec_issue_info =
};
/* Neoverse V1 costs for vector insn classes. */
-static const struct cpu_vector_cost neoversev1_vector_cost =
+static struct cpu_vector_cost neoversev1_vector_cost =
{
1, /* scalar_int_stmt_cost */
2, /* scalar_fp_stmt_cost */
@@ -197,7 +197,7 @@ static const struct cpu_vector_cost neoversev1_vector_cost =
&neoversev1_vec_issue_info /* issue_info */
};
-static const struct tune_params neoversev1_tunings =
+static struct tune_params neoversev1_tunings =
{
&cortexa76_extra_costs,
&neoversev1_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/neoversev2.h
b/gcc/config/aarch64/tuning_models/neoversev2.h
index b000fb46570..7a12ab997d1 100644
--- a/gcc/config/aarch64/tuning_models/neoversev2.h
+++ b/gcc/config/aarch64/tuning_models/neoversev2.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_regmove_cost neoversev2_regmove_cost =
+static struct cpu_regmove_cost neoversev2_regmove_cost =
{
1, /* GP2GP */
/* Spilling to int<->fp instead of memory is recommended so set
@@ -32,7 +32,7 @@ static const struct cpu_regmove_cost neoversev2_regmove_cost =
2 /* FP2FP */
};
-static const advsimd_vec_cost neoversev2_advsimd_vector_cost =
+static advsimd_vec_cost neoversev2_advsimd_vector_cost =
{
2, /* int_stmt_cost */
2, /* fp_stmt_cost */
@@ -63,7 +63,7 @@ static const advsimd_vec_cost neoversev2_advsimd_vector_cost =
1 /* store_cost */
};
-static const sve_vec_cost neoversev2_sve_vector_cost =
+static sve_vec_cost neoversev2_sve_vector_cost =
{
{
2, /* int_stmt_cost */
@@ -122,7 +122,7 @@ static const sve_vec_cost neoversev2_sve_vector_cost =
3 /* scatter_store_elt_cost */
};
-static const aarch64_scalar_vec_issue_info neoversev2_scalar_issue_info =
+static aarch64_scalar_vec_issue_info neoversev2_scalar_issue_info =
{
3, /* loads_stores_per_cycle */
2, /* stores_per_cycle */
@@ -131,7 +131,7 @@ static const aarch64_scalar_vec_issue_info
neoversev2_scalar_issue_info =
1 /* fp_simd_store_general_ops */
};
-static const aarch64_advsimd_vec_issue_info neoversev2_advsimd_issue_info =
+static aarch64_advsimd_vec_issue_info neoversev2_advsimd_issue_info =
{
{
3, /* loads_stores_per_cycle */
@@ -145,7 +145,7 @@ static const aarch64_advsimd_vec_issue_info
neoversev2_advsimd_issue_info =
3 /* ld4_st4_general_ops */
};
-static const aarch64_sve_vec_issue_info neoversev2_sve_issue_info =
+static aarch64_sve_vec_issue_info neoversev2_sve_issue_info =
{
{
{
@@ -167,7 +167,7 @@ static const aarch64_sve_vec_issue_info
neoversev2_sve_issue_info =
1 /* gather_scatter_pair_pred_ops */
};
-static const aarch64_vec_issue_info neoversev2_vec_issue_info =
+static aarch64_vec_issue_info neoversev2_vec_issue_info =
{
&neoversev2_scalar_issue_info,
&neoversev2_advsimd_issue_info,
@@ -175,7 +175,7 @@ static const aarch64_vec_issue_info
neoversev2_vec_issue_info =
};
/* Neoversev2 costs for vector insn classes. */
-static const struct cpu_vector_cost neoversev2_vector_cost =
+static struct cpu_vector_cost neoversev2_vector_cost =
{
1, /* scalar_int_stmt_cost */
2, /* scalar_fp_stmt_cost */
@@ -188,7 +188,7 @@ static const struct cpu_vector_cost neoversev2_vector_cost =
&neoversev2_vec_issue_info /* issue_info */
};
-static const struct tune_params neoversev2_tunings =
+static struct tune_params neoversev2_tunings =
{
&cortexa76_extra_costs,
&generic_armv9_a_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/neoversev3.h
b/gcc/config/aarch64/tuning_models/neoversev3.h
index ad3cd222512..187e7a21de2 100644
--- a/gcc/config/aarch64/tuning_models/neoversev3.h
+++ b/gcc/config/aarch64/tuning_models/neoversev3.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_regmove_cost neoversev3_regmove_cost =
+static struct cpu_regmove_cost neoversev3_regmove_cost =
{
3, /* GP2GP */
/* Spilling to int<->fp instead of memory is recommended so set
@@ -32,7 +32,7 @@ static const struct cpu_regmove_cost neoversev3_regmove_cost =
4 /* FP2FP */
};
-static const advsimd_vec_cost neoversev3_advsimd_vector_cost =
+static advsimd_vec_cost neoversev3_advsimd_vector_cost =
{
2, /* int_stmt_cost */
2, /* fp_stmt_cost */
@@ -63,7 +63,7 @@ static const advsimd_vec_cost neoversev3_advsimd_vector_cost =
1 /* store_cost */
};
-static const sve_vec_cost neoversev3_sve_vector_cost =
+static sve_vec_cost neoversev3_sve_vector_cost =
{
{
2, /* int_stmt_cost */
@@ -122,7 +122,7 @@ static const sve_vec_cost neoversev3_sve_vector_cost =
1 /* scatter_store_elt_cost */
};
-static const aarch64_scalar_vec_issue_info neoversev3_scalar_issue_info =
+static aarch64_scalar_vec_issue_info neoversev3_scalar_issue_info =
{
3, /* loads_stores_per_cycle */
2, /* stores_per_cycle */
@@ -131,7 +131,7 @@ static const aarch64_scalar_vec_issue_info
neoversev3_scalar_issue_info =
1 /* fp_simd_store_general_ops */
};
-static const aarch64_advsimd_vec_issue_info neoversev3_advsimd_issue_info =
+static aarch64_advsimd_vec_issue_info neoversev3_advsimd_issue_info =
{
{
3, /* loads_stores_per_cycle */
@@ -145,7 +145,7 @@ static const aarch64_advsimd_vec_issue_info
neoversev3_advsimd_issue_info =
3 /* ld4_st4_general_ops */
};
-static const aarch64_sve_vec_issue_info neoversev3_sve_issue_info =
+static aarch64_sve_vec_issue_info neoversev3_sve_issue_info =
{
{
{
@@ -167,7 +167,7 @@ static const aarch64_sve_vec_issue_info
neoversev3_sve_issue_info =
1 /* gather_scatter_pair_pred_ops */
};
-static const aarch64_vec_issue_info neoversev3_vec_issue_info =
+static aarch64_vec_issue_info neoversev3_vec_issue_info =
{
&neoversev3_scalar_issue_info,
&neoversev3_advsimd_issue_info,
@@ -175,7 +175,7 @@ static const aarch64_vec_issue_info
neoversev3_vec_issue_info =
};
/* Neoversev3 costs for vector insn classes. */
-static const struct cpu_vector_cost neoversev3_vector_cost =
+static struct cpu_vector_cost neoversev3_vector_cost =
{
1, /* scalar_int_stmt_cost */
2, /* scalar_fp_stmt_cost */
@@ -188,7 +188,7 @@ static const struct cpu_vector_cost neoversev3_vector_cost =
&neoversev3_vec_issue_info /* issue_info */
};
-static const struct tune_params neoversev3_tunings =
+static struct tune_params neoversev3_tunings =
{
&cortexa76_extra_costs,
&generic_armv9_a_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/neoversev3ae.h
b/gcc/config/aarch64/tuning_models/neoversev3ae.h
index a0adef00824..d5ec42ac995 100644
--- a/gcc/config/aarch64/tuning_models/neoversev3ae.h
+++ b/gcc/config/aarch64/tuning_models/neoversev3ae.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_regmove_cost neoversev3ae_regmove_cost =
+static struct cpu_regmove_cost neoversev3ae_regmove_cost =
{
3, /* GP2GP */
/* Spilling to int<->fp instead of memory is recommended so set
@@ -32,7 +32,7 @@ static const struct cpu_regmove_cost
neoversev3ae_regmove_cost =
4 /* FP2FP */
};
-static const advsimd_vec_cost neoversev3ae_advsimd_vector_cost =
+static advsimd_vec_cost neoversev3ae_advsimd_vector_cost =
{
2, /* int_stmt_cost */
2, /* fp_stmt_cost */
@@ -63,7 +63,7 @@ static const advsimd_vec_cost
neoversev3ae_advsimd_vector_cost =
1 /* store_cost */
};
-static const sve_vec_cost neoversev3ae_sve_vector_cost =
+static sve_vec_cost neoversev3ae_sve_vector_cost =
{
{
2, /* int_stmt_cost */
@@ -122,7 +122,7 @@ static const sve_vec_cost neoversev3ae_sve_vector_cost =
1 /* scatter_store_elt_cost */
};
-static const aarch64_scalar_vec_issue_info neoversev3ae_scalar_issue_info =
+static aarch64_scalar_vec_issue_info neoversev3ae_scalar_issue_info =
{
3, /* loads_stores_per_cycle */
2, /* stores_per_cycle */
@@ -131,7 +131,7 @@ static const aarch64_scalar_vec_issue_info
neoversev3ae_scalar_issue_info =
1 /* fp_simd_store_general_ops */
};
-static const aarch64_advsimd_vec_issue_info neoversev3ae_advsimd_issue_info =
+static aarch64_advsimd_vec_issue_info neoversev3ae_advsimd_issue_info =
{
{
3, /* loads_stores_per_cycle */
@@ -145,7 +145,7 @@ static const aarch64_advsimd_vec_issue_info
neoversev3ae_advsimd_issue_info =
3 /* ld4_st4_general_ops */
};
-static const aarch64_sve_vec_issue_info neoversev3ae_sve_issue_info =
+static aarch64_sve_vec_issue_info neoversev3ae_sve_issue_info =
{
{
{
@@ -167,7 +167,7 @@ static const aarch64_sve_vec_issue_info
neoversev3ae_sve_issue_info =
1 /* gather_scatter_pair_pred_ops */
};
-static const aarch64_vec_issue_info neoversev3ae_vec_issue_info =
+static aarch64_vec_issue_info neoversev3ae_vec_issue_info =
{
&neoversev3ae_scalar_issue_info,
&neoversev3ae_advsimd_issue_info,
@@ -175,7 +175,7 @@ static const aarch64_vec_issue_info
neoversev3ae_vec_issue_info =
};
/* Neoversev3ae costs for vector insn classes. */
-static const struct cpu_vector_cost neoversev3ae_vector_cost =
+static struct cpu_vector_cost neoversev3ae_vector_cost =
{
1, /* scalar_int_stmt_cost */
2, /* scalar_fp_stmt_cost */
@@ -188,7 +188,7 @@ static const struct cpu_vector_cost
neoversev3ae_vector_cost =
&neoversev3ae_vec_issue_info /* issue_info */
};
-static const struct tune_params neoversev3ae_tunings =
+static struct tune_params neoversev3ae_tunings =
{
&cortexa76_extra_costs,
&generic_armv9_a_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/qdf24xx.h
b/gcc/config/aarch64/tuning_models/qdf24xx.h
index 583d30a4d17..814a01bcfe9 100644
--- a/gcc/config/aarch64/tuning_models/qdf24xx.h
+++ b/gcc/config/aarch64/tuning_models/qdf24xx.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_addrcost_table qdf24xx_addrcost_table =
+static struct cpu_addrcost_table qdf24xx_addrcost_table =
{
{
1, /* hi */
@@ -40,7 +40,7 @@ static const struct cpu_addrcost_table qdf24xx_addrcost_table
=
2, /* imm_offset */
};
-static const struct cpu_regmove_cost qdf24xx_regmove_cost =
+static struct cpu_regmove_cost qdf24xx_regmove_cost =
{
2, /* GP2GP */
/* Avoid the use of int<->fp moves for spilling. */
@@ -49,7 +49,7 @@ static const struct cpu_regmove_cost qdf24xx_regmove_cost =
4 /* FP2FP */
};
-static const advsimd_vec_cost qdf24xx_advsimd_vector_cost =
+static advsimd_vec_cost qdf24xx_advsimd_vector_cost =
{
1, /* int_stmt_cost */
3, /* fp_stmt_cost */
@@ -74,7 +74,7 @@ static const advsimd_vec_cost qdf24xx_advsimd_vector_cost =
};
/* QDF24XX costs for vector insn classes. */
-static const struct cpu_vector_cost qdf24xx_vector_cost =
+static struct cpu_vector_cost qdf24xx_vector_cost =
{
1, /* scalar_int_stmt_cost */
1, /* scalar_fp_stmt_cost */
@@ -87,7 +87,7 @@ static const struct cpu_vector_cost qdf24xx_vector_cost =
nullptr /* issue_info */
};
-static const cpu_prefetch_tune qdf24xx_prefetch_tune =
+static cpu_prefetch_tune qdf24xx_prefetch_tune =
{
4, /* num_slots */
32, /* l1_cache_size */
@@ -98,7 +98,7 @@ static const cpu_prefetch_tune qdf24xx_prefetch_tune =
3 /* default_opt_level */
};
-static const struct tune_params qdf24xx_tunings =
+static struct tune_params qdf24xx_tunings =
{
&qdf24xx_extra_costs,
&qdf24xx_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/saphira.h
b/gcc/config/aarch64/tuning_models/saphira.h
index 684f3951a60..f48255390c9 100644
--- a/gcc/config/aarch64/tuning_models/saphira.h
+++ b/gcc/config/aarch64/tuning_models/saphira.h
@@ -24,7 +24,7 @@
/* Tuning structure for the Qualcomm Saphira core. Default to falkor values
for now. */
-static const struct tune_params saphira_tunings =
+static struct tune_params saphira_tunings =
{
&generic_extra_costs,
&generic_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/thunderx.h
b/gcc/config/aarch64/tuning_models/thunderx.h
index d79c1391b8c..4f87b0e1a50 100644
--- a/gcc/config/aarch64/tuning_models/thunderx.h
+++ b/gcc/config/aarch64/tuning_models/thunderx.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_regmove_cost thunderx_regmove_cost =
+static struct cpu_regmove_cost thunderx_regmove_cost =
{
2, /* GP2GP */
2, /* GP2FP */
@@ -30,7 +30,7 @@ static const struct cpu_regmove_cost thunderx_regmove_cost =
4 /* FP2FP */
};
-static const advsimd_vec_cost thunderx_advsimd_vector_cost =
+static advsimd_vec_cost thunderx_advsimd_vector_cost =
{
4, /* int_stmt_cost */
1, /* fp_stmt_cost */
@@ -55,7 +55,7 @@ static const advsimd_vec_cost thunderx_advsimd_vector_cost =
};
/* ThunderX costs for vector insn classes. */
-static const struct cpu_vector_cost thunderx_vector_cost =
+static struct cpu_vector_cost thunderx_vector_cost =
{
1, /* scalar_int_stmt_cost */
1, /* scalar_fp_stmt_cost */
@@ -68,7 +68,7 @@ static const struct cpu_vector_cost thunderx_vector_cost =
nullptr /* issue_info */
};
-static const cpu_prefetch_tune thunderx_prefetch_tune =
+static cpu_prefetch_tune thunderx_prefetch_tune =
{
8, /* num_slots */
32, /* l1_cache_size */
@@ -79,7 +79,7 @@ static const cpu_prefetch_tune thunderx_prefetch_tune =
-1 /* default_opt_level */
};
-static const struct tune_params thunderx_tunings =
+static struct tune_params thunderx_tunings =
{
&thunderx_extra_costs,
&generic_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/thunderx2t99.h
b/gcc/config/aarch64/tuning_models/thunderx2t99.h
index 513c6158084..2577bbd7535 100644
--- a/gcc/config/aarch64/tuning_models/thunderx2t99.h
+++ b/gcc/config/aarch64/tuning_models/thunderx2t99.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_addrcost_table thunderx2t99_addrcost_table =
+static struct cpu_addrcost_table thunderx2t99_addrcost_table =
{
{
1, /* hi */
@@ -40,7 +40,7 @@ static const struct cpu_addrcost_table
thunderx2t99_addrcost_table =
0, /* imm_offset */
};
-static const struct cpu_regmove_cost thunderx2t99_regmove_cost =
+static struct cpu_regmove_cost thunderx2t99_regmove_cost =
{
1, /* GP2GP */
/* Avoid the use of int<->fp moves for spilling. */
@@ -49,7 +49,7 @@ static const struct cpu_regmove_cost
thunderx2t99_regmove_cost =
3, /* FP2FP */
};
-static const advsimd_vec_cost thunderx2t99_advsimd_vector_cost =
+static advsimd_vec_cost thunderx2t99_advsimd_vector_cost =
{
4, /* int_stmt_cost */
5, /* fp_stmt_cost */
@@ -74,7 +74,7 @@ static const advsimd_vec_cost
thunderx2t99_advsimd_vector_cost =
};
/* Costs for vector insn classes for Vulcan. */
-static const struct cpu_vector_cost thunderx2t99_vector_cost =
+static struct cpu_vector_cost thunderx2t99_vector_cost =
{
1, /* scalar_int_stmt_cost */
6, /* scalar_fp_stmt_cost */
@@ -87,7 +87,7 @@ static const struct cpu_vector_cost thunderx2t99_vector_cost =
nullptr /* issue_info */
};
-static const cpu_prefetch_tune thunderx2t99_prefetch_tune =
+static cpu_prefetch_tune thunderx2t99_prefetch_tune =
{
8, /* num_slots */
32, /* l1_cache_size */
@@ -98,7 +98,7 @@ static const cpu_prefetch_tune thunderx2t99_prefetch_tune =
-1 /* default_opt_level */
};
-static const struct tune_params thunderx2t99_tunings =
+static struct tune_params thunderx2t99_tunings =
{
&thunderx2t99_extra_costs,
&thunderx2t99_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/thunderx3t110.h
b/gcc/config/aarch64/tuning_models/thunderx3t110.h
index a2547b8e54d..c9f2dc74c3e 100644
--- a/gcc/config/aarch64/tuning_models/thunderx3t110.h
+++ b/gcc/config/aarch64/tuning_models/thunderx3t110.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_addrcost_table thunderx3t110_addrcost_table =
+static struct cpu_addrcost_table thunderx3t110_addrcost_table =
{
{
1, /* hi */
@@ -40,7 +40,7 @@ static const struct cpu_addrcost_table
thunderx3t110_addrcost_table =
0, /* imm_offset */
};
-static const struct cpu_regmove_cost thunderx3t110_regmove_cost =
+static struct cpu_regmove_cost thunderx3t110_regmove_cost =
{
1, /* GP2GP */
/* Avoid the use of int<->fp moves for spilling. */
@@ -49,7 +49,7 @@ static const struct cpu_regmove_cost
thunderx3t110_regmove_cost =
4 /* FP2FP */
};
-static const advsimd_vec_cost thunderx3t110_advsimd_vector_cost =
+static advsimd_vec_cost thunderx3t110_advsimd_vector_cost =
{
5, /* int_stmt_cost */
5, /* fp_stmt_cost */
@@ -73,7 +73,7 @@ static const advsimd_vec_cost
thunderx3t110_advsimd_vector_cost =
4 /* store_cost */
};
-static const struct cpu_vector_cost thunderx3t110_vector_cost =
+static struct cpu_vector_cost thunderx3t110_vector_cost =
{
1, /* scalar_int_stmt_cost */
5, /* scalar_fp_stmt_cost */
@@ -86,7 +86,7 @@ static const struct cpu_vector_cost thunderx3t110_vector_cost
=
nullptr /* issue_info */
};
-static const cpu_prefetch_tune thunderx3t110_prefetch_tune =
+static cpu_prefetch_tune thunderx3t110_prefetch_tune =
{
8, /* num_slots */
32, /* l1_cache_size */
@@ -97,7 +97,7 @@ static const cpu_prefetch_tune thunderx3t110_prefetch_tune =
-1 /* default_opt_level */
};
-static const struct tune_params thunderx3t110_tunings =
+static struct tune_params thunderx3t110_tunings =
{
&thunderx3t110_extra_costs,
&thunderx3t110_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/thunderxt88.h
b/gcc/config/aarch64/tuning_models/thunderxt88.h
index 6be5c526fc1..80ae8bfd4e4 100644
--- a/gcc/config/aarch64/tuning_models/thunderxt88.h
+++ b/gcc/config/aarch64/tuning_models/thunderxt88.h
@@ -23,7 +23,7 @@
#include "generic.h"
#include "thunderx.h"
-static const cpu_prefetch_tune thunderxt88_prefetch_tune =
+static cpu_prefetch_tune thunderxt88_prefetch_tune =
{
8, /* num_slots */
32, /* l1_cache_size */
@@ -34,7 +34,7 @@ static const cpu_prefetch_tune thunderxt88_prefetch_tune =
3 /* default_opt_level */
};
-static const struct tune_params thunderxt88_tunings =
+static struct tune_params thunderxt88_tunings =
{
&thunderx_extra_costs,
&generic_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/tsv110.h
b/gcc/config/aarch64/tuning_models/tsv110.h
index 458286e0e80..88758262c45 100644
--- a/gcc/config/aarch64/tuning_models/tsv110.h
+++ b/gcc/config/aarch64/tuning_models/tsv110.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_addrcost_table tsv110_addrcost_table =
+static struct cpu_addrcost_table tsv110_addrcost_table =
{
{
1, /* hi */
@@ -40,7 +40,7 @@ static const struct cpu_addrcost_table tsv110_addrcost_table =
0, /* imm_offset */
};
-static const struct cpu_regmove_cost tsv110_regmove_cost =
+static struct cpu_regmove_cost tsv110_regmove_cost =
{
1, /* GP2GP */
/* Avoid the use of slow int<->fp moves for spilling by setting
@@ -50,7 +50,7 @@ static const struct cpu_regmove_cost tsv110_regmove_cost =
2 /* FP2FP */
};
-static const advsimd_vec_cost tsv110_advsimd_vector_cost =
+static advsimd_vec_cost tsv110_advsimd_vector_cost =
{
2, /* int_stmt_cost */
2, /* fp_stmt_cost */
@@ -74,7 +74,7 @@ static const advsimd_vec_cost tsv110_advsimd_vector_cost =
1 /* store_cost */
};
-static const struct cpu_vector_cost tsv110_vector_cost =
+static struct cpu_vector_cost tsv110_vector_cost =
{
1, /* scalar_int_stmt_cost */
1, /* scalar_fp_stmt_cost */
@@ -87,7 +87,7 @@ static const struct cpu_vector_cost tsv110_vector_cost =
nullptr /* issue_info */
};
-static const cpu_prefetch_tune tsv110_prefetch_tune =
+static cpu_prefetch_tune tsv110_prefetch_tune =
{
0, /* num_slots */
64, /* l1_cache_size */
@@ -98,7 +98,7 @@ static const cpu_prefetch_tune tsv110_prefetch_tune =
-1 /* default_opt_level */
};
-static const struct tune_params tsv110_tunings =
+static struct tune_params tsv110_tunings =
{
&tsv110_extra_costs,
&tsv110_addrcost_table,
diff --git a/gcc/config/aarch64/tuning_models/xgene1.h
b/gcc/config/aarch64/tuning_models/xgene1.h
index b4f01ee92f5..7ebcb37195b 100644
--- a/gcc/config/aarch64/tuning_models/xgene1.h
+++ b/gcc/config/aarch64/tuning_models/xgene1.h
@@ -22,7 +22,7 @@
#include "generic.h"
-static const struct cpu_addrcost_table xgene1_addrcost_table =
+static struct cpu_addrcost_table xgene1_addrcost_table =
{
{
1, /* hi */
@@ -40,7 +40,7 @@ static const struct cpu_addrcost_table xgene1_addrcost_table =
0, /* imm_offset */
};
-static const struct cpu_regmove_cost xgene1_regmove_cost =
+static struct cpu_regmove_cost xgene1_regmove_cost =
{
1, /* GP2GP */
/* Avoid the use of slow int<->fp moves for spilling by setting
@@ -50,7 +50,7 @@ static const struct cpu_regmove_cost xgene1_regmove_cost =
2 /* FP2FP */
};
-static const advsimd_vec_cost xgene1_advsimd_vector_cost =
+static advsimd_vec_cost xgene1_advsimd_vector_cost =
{
2, /* int_stmt_cost */
2, /* fp_stmt_cost */
@@ -75,7 +75,7 @@ static const advsimd_vec_cost xgene1_advsimd_vector_cost =
};
/* Generic costs for vector insn classes. */
-static const struct cpu_vector_cost xgene1_vector_cost =
+static struct cpu_vector_cost xgene1_vector_cost =
{
1, /* scalar_int_stmt_cost */
1, /* scalar_fp_stmt_cost */
@@ -89,14 +89,14 @@ static const struct cpu_vector_cost xgene1_vector_cost =
};
/* Approximation modes for X-Gene 1. */
-static const cpu_approx_modes xgene1_approx_modes =
+static cpu_approx_modes xgene1_approx_modes =
{
AARCH64_APPROX_NONE, /* division */
AARCH64_APPROX_NONE, /* sqrt */
AARCH64_APPROX_ALL /* recip_sqrt */
};
-static const cpu_prefetch_tune xgene1_prefetch_tune =
+static cpu_prefetch_tune xgene1_prefetch_tune =
{
8, /* num_slots */
32, /* l1_cache_size */
@@ -107,7 +107,7 @@ static const cpu_prefetch_tune xgene1_prefetch_tune =
-1 /* default_opt_level */
};
-static const struct tune_params xgene1_tunings =
+static struct tune_params xgene1_tunings =
{
&xgene1_extra_costs,
&xgene1_addrcost_table,
diff --git a/gcc/config/arm/aarch-common-protos.h
b/gcc/config/arm/aarch-common-protos.h
index 077387b9f90..784feb48efb 100644
--- a/gcc/config/arm/aarch-common-protos.h
+++ b/gcc/config/arm/aarch-common-protos.h
@@ -57,33 +57,33 @@ extern bool aarch_fun_is_indirect_return (rtx_insn *);
Costs may not have a negative value. */
struct alu_cost_table
{
- const int arith; /* ADD/SUB. */
- const int logical; /* AND/ORR/EOR/BIC, etc. */
- const int shift; /* Simple shift. */
- const int shift_reg; /* Simple shift by reg. */
- const int arith_shift; /* Additional when arith also shifts... */
- const int arith_shift_reg; /* ... and when the shift is by a reg. */
- const int log_shift; /* Additional when logic also shifts... */
- const int log_shift_reg; /* ... and when the shift is by a reg. */
- const int extend; /* Zero/sign extension. */
- const int extend_arith; /* Extend and arith. */
- const int bfi; /* Bit-field insert. */
- const int bfx; /* Bit-field extraction. */
- const int clz; /* Count Leading Zeros. */
- const int rev; /* Reverse bits/bytes. */
- const int non_exec; /* Extra cost when not executing insn. */
- const bool non_exec_costs_exec; /* True if non-execution must add the exec
+ int arith; /* ADD/SUB. */
+ int logical; /* AND/ORR/EOR/BIC, etc. */
+ int shift; /* Simple shift. */
+ int shift_reg; /* Simple shift by reg. */
+ int arith_shift; /* Additional when arith also shifts... */
+ int arith_shift_reg; /* ... and when the shift is by a reg. */
+ int log_shift; /* Additional when logic also shifts... */
+ int log_shift_reg; /* ... and when the shift is by a reg. */
+ int extend; /* Zero/sign extension. */
+ int extend_arith; /* Extend and arith. */
+ int bfi; /* Bit-field insert. */
+ int bfx; /* Bit-field extraction. */
+ int clz; /* Count Leading Zeros. */
+ int rev; /* Reverse bits/bytes. */
+ int non_exec; /* Extra cost when not executing insn. */
+ bool non_exec_costs_exec; /* True if non-execution must add the exec
cost. */
};
struct mult_cost_table
{
- const int simple;
- const int flag_setting; /* Additional cost if multiply sets flags. */
- const int extend;
- const int add;
- const int extend_add;
- const int idiv;
+ int simple;
+ int flag_setting; /* Additional cost if multiply sets flags. */
+ int extend;
+ int add;
+ int extend_add;
+ int idiv;
};
/* Calculations of LDM costs are complex. We assume an initial cost
@@ -98,60 +98,60 @@ struct mult_cost_table
*/
struct mem_cost_table
{
- const int load;
- const int load_sign_extend; /* Additional to load cost. */
- const int ldrd; /* Cost of LDRD. */
- const int ldm_1st;
- const int ldm_regs_per_insn_1st;
- const int ldm_regs_per_insn_subsequent;
- const int loadf; /* SFmode. */
- const int loadd; /* DFmode. */
- const int load_unaligned; /* Extra for unaligned loads. */
- const int store;
- const int strd;
- const int stm_1st;
- const int stm_regs_per_insn_1st;
- const int stm_regs_per_insn_subsequent;
- const int storef; /* SFmode. */
- const int stored; /* DFmode. */
- const int store_unaligned; /* Extra for unaligned stores. */
- const int loadv; /* Vector load. */
- const int storev; /* Vector store. */
+ int load;
+ int load_sign_extend; /* Additional to load cost. */
+ int ldrd; /* Cost of LDRD. */
+ int ldm_1st;
+ int ldm_regs_per_insn_1st;
+ int ldm_regs_per_insn_subsequent;
+ int loadf; /* SFmode. */
+ int loadd; /* DFmode. */
+ int load_unaligned; /* Extra for unaligned loads. */
+ int store;
+ int strd;
+ int stm_1st;
+ int stm_regs_per_insn_1st;
+ int stm_regs_per_insn_subsequent;
+ int storef; /* SFmode. */
+ int stored; /* DFmode. */
+ int store_unaligned; /* Extra for unaligned stores. */
+ int loadv; /* Vector load. */
+ int storev; /* Vector store. */
};
struct fp_cost_table
{
- const int div;
- const int mult;
- const int mult_addsub; /* Non-fused. */
- const int fma; /* Fused. */
- const int addsub;
- const int fpconst; /* Immediate. */
- const int neg; /* NEG and ABS. */
- const int compare;
- const int widen; /* Widen to this size. */
- const int narrow; /* Narrow from this size. */
- const int toint;
- const int fromint;
- const int roundint; /* V8 round to integral, remains FP format. */
+ int div;
+ int mult;
+ int mult_addsub; /* Non-fused. */
+ int fma; /* Fused. */
+ int addsub;
+ int fpconst; /* Immediate. */
+ int neg; /* NEG and ABS. */
+ int compare;
+ int widen; /* Widen to this size. */
+ int narrow; /* Narrow from this size. */
+ int toint;
+ int fromint;
+ int roundint; /* V8 round to integral, remains FP format. */
};
struct vector_cost_table
{
- const int alu;
- const int mult;
- const int movi;
- const int dup;
- const int extract;
+ int alu;
+ int mult;
+ int movi;
+ int dup;
+ int extract;
};
struct cpu_cost_table
{
- const struct alu_cost_table alu;
- const struct mult_cost_table mult[2]; /* SImode and DImode. */
- const struct mem_cost_table ldst;
- const struct fp_cost_table fp[2]; /* SFmode and DFmode. */
- const struct vector_cost_table vect;
+ struct alu_cost_table alu;
+ struct mult_cost_table mult[2]; /* SImode and DImode. */
+ struct mem_cost_table ldst;
+ struct fp_cost_table fp[2]; /* SFmode and DFmode. */
+ struct vector_cost_table vect;
};
rtx_insn *arm_md_asm_adjust (vec<rtx> &outputs, vec<rtx> & /*inputs*/,
diff --git a/gcc/config/arm/aarch-cost-tables.h
b/gcc/config/arm/aarch-cost-tables.h
index c7a14b3750d..a733ebaac58 100644
--- a/gcc/config/arm/aarch-cost-tables.h
+++ b/gcc/config/arm/aarch-cost-tables.h
@@ -22,7 +22,7 @@
#ifndef GCC_AARCH_COST_TABLES_H
#define GCC_AARCH_COST_TABLES_H
-const struct cpu_cost_table generic_extra_costs =
+struct cpu_cost_table generic_extra_costs =
{
/* ALU */
{
@@ -129,7 +129,7 @@ const struct cpu_cost_table generic_extra_costs =
}
};
-const struct cpu_cost_table cortexa53_extra_costs =
+struct cpu_cost_table cortexa53_extra_costs =
{
/* ALU */
{
@@ -236,7 +236,7 @@ const struct cpu_cost_table cortexa53_extra_costs =
}
};
-const struct cpu_cost_table cortexa57_extra_costs =
+struct cpu_cost_table cortexa57_extra_costs =
{
/* ALU */
{
@@ -343,7 +343,7 @@ const struct cpu_cost_table cortexa57_extra_costs =
}
};
-const struct cpu_cost_table cortexa76_extra_costs =
+struct cpu_cost_table cortexa76_extra_costs =
{
/* ALU */
{
@@ -450,7 +450,7 @@ const struct cpu_cost_table cortexa76_extra_costs =
}
};
-const struct cpu_cost_table exynosm1_extra_costs =
+struct cpu_cost_table exynosm1_extra_costs =
{
/* ALU */
{
@@ -557,7 +557,7 @@ const struct cpu_cost_table exynosm1_extra_costs =
}
};
-const struct cpu_cost_table xgene1_extra_costs =
+struct cpu_cost_table xgene1_extra_costs =
{
/* ALU */
{
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 254c7310794..61d716a0447 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -337,7 +337,7 @@ struct addr_mode_cost_table
struct tune_params
{
- const struct cpu_cost_table *insn_extra_cost;
+ struct cpu_cost_table *insn_extra_cost;
const struct addr_mode_cost_table *addr_mode_costs;
bool (*sched_adjust_cost) (rtx_insn *, int, rtx_insn *, int *);
int (*branch_cost) (bool, bool);
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index a95ddf8201f..9727e158589 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -1103,7 +1103,7 @@ struct cpu_vec_costs arm_default_vec_cost = {
-const struct cpu_cost_table cortexa9_extra_costs =
+struct cpu_cost_table cortexa9_extra_costs =
{
/* ALU */
{
@@ -1210,7 +1210,7 @@ const struct cpu_cost_table cortexa9_extra_costs =
}
};
-const struct cpu_cost_table cortexa8_extra_costs =
+struct cpu_cost_table cortexa8_extra_costs =
{
/* ALU */
{
@@ -1317,7 +1317,7 @@ const struct cpu_cost_table cortexa8_extra_costs =
}
};
-const struct cpu_cost_table cortexa5_extra_costs =
+struct cpu_cost_table cortexa5_extra_costs =
{
/* ALU */
{
@@ -1426,7 +1426,7 @@ const struct cpu_cost_table cortexa5_extra_costs =
};
-const struct cpu_cost_table cortexa7_extra_costs =
+struct cpu_cost_table cortexa7_extra_costs =
{
/* ALU */
{
@@ -1534,7 +1534,7 @@ const struct cpu_cost_table cortexa7_extra_costs =
}
};
-const struct cpu_cost_table cortexa12_extra_costs =
+struct cpu_cost_table cortexa12_extra_costs =
{
/* ALU */
{
@@ -1641,7 +1641,7 @@ const struct cpu_cost_table cortexa12_extra_costs =
}
};
-const struct cpu_cost_table cortexa15_extra_costs =
+struct cpu_cost_table cortexa15_extra_costs =
{
/* ALU */
{
@@ -1748,7 +1748,7 @@ const struct cpu_cost_table cortexa15_extra_costs =
}
};
-const struct cpu_cost_table v7m_extra_costs =
+struct cpu_cost_table v7m_extra_costs =
{
/* ALU */
{
@@ -10175,7 +10175,7 @@ shifter_op_p (rtx op, rtx *shift_reg)
static bool
arm_unspec_cost (rtx x, enum rtx_code /* outer_code */, bool speed_p, int
*cost)
{
- const struct cpu_cost_table *extra_cost = current_tune->insn_extra_cost;
+ struct cpu_cost_table *extra_cost = current_tune->insn_extra_cost;
rtx_code code = GET_CODE (x);
gcc_assert (code == UNSPEC || code == UNSPEC_VOLATILE);
@@ -10260,7 +10260,7 @@ arm_unspec_cost (rtx x, enum rtx_code /* outer_code */,
bool speed_p, int *cost)
considering the costs of the addressing mode and memory access
separately. */
static bool
-arm_mem_costs (rtx x, const struct cpu_cost_table *extra_cost,
+arm_mem_costs (rtx x, struct cpu_cost_table *extra_cost,
int *cost, bool speed_p)
{
machine_mode mode = GET_MODE (x);
@@ -10405,7 +10405,7 @@ arm_bfi_p (rtx x, rtx *sub0, rtx *sub1)
the size will eventually be. */
static bool
arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
- const struct cpu_cost_table *extra_cost,
+ struct cpu_cost_table *extra_cost,
int *cost, bool speed_p)
{
machine_mode mode = GET_MODE (x);
--
2.44.0
