Add the `+cmpbr` option to enable the FEAT_CMPBR architectural
extension.
gcc/ChangeLog:
* config/aarch64/aarch64-option-extensions.def (cmpbr): New
option.
* config/aarch64/aarch64.h (TARGET_CMPBR): New macro.
* doc/invoke.texi (cmpbr): New option.
---
gcc/config/aarch64/aarch64-option-extensions.def | 2 ++
gcc/config/aarch64/aarch64.h | 3 +++
gcc/doc/invoke.texi | 3 +++
3 files changed, 8 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def
b/gcc/config/aarch64/aarch64-option-extensions.def
index dbbb021f05a..1c3e69799f5 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -249,6 +249,8 @@ AARCH64_OPT_EXTENSION("mops", MOPS, (), (), (), "mops")
AARCH64_OPT_EXTENSION("cssc", CSSC, (), (), (), "cssc")
+AARCH64_OPT_EXTENSION("cmpbr", CMPBR, (), (), (), "cmpbr")
+
AARCH64_OPT_EXTENSION("lse128", LSE128, (LSE), (), (), "lse128")
AARCH64_OPT_EXTENSION("d128", D128, (LSE128), (), (), "d128")
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index e8bd8c73c12..d5c4a42e96d 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -202,326 +202,329 @@ constexpr auto AARCH64_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
= AARCH64_ISA_MODE_SM_OFF;
constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
= aarch64_feature_flags (AARCH64_DEFAULT_ISA_MODE);
#endif
/* Macros to test ISA flags.
There is intentionally no macro for AARCH64_FL_CRYPTO, since this flag bit
is not always set when its constituent features are present.
Check (TARGET_AES && TARGET_SHA2) instead. */
#define AARCH64_HAVE_ISA(X) (bool (aarch64_isa_flags & AARCH64_FL_##X))
#define AARCH64_ISA_MODE ((aarch64_isa_flags & AARCH64_FL_ISA_MODES).val[0])
/* The current function is a normal non-streaming function. */
#define TARGET_NON_STREAMING AARCH64_HAVE_ISA (SM_OFF)
/* The current function has a streaming body. */
#define TARGET_STREAMING AARCH64_HAVE_ISA (SM_ON)
/* The current function has a streaming-compatible body. */
#define TARGET_STREAMING_COMPATIBLE \
((aarch64_isa_flags & AARCH64_FL_SM_STATE) == 0)
/* PSTATE.ZA is enabled in the current function body. */
#define TARGET_ZA AARCH64_HAVE_ISA (ZA_ON)
/* AdvSIMD is supported in the default configuration, unless disabled by
-mgeneral-regs-only or by the +nosimd extension. The set of available
instructions is then subdivided into:
- the "base" set, available both in SME streaming mode and in
non-streaming mode
- the full set, available only in non-streaming mode. */
#define TARGET_BASE_SIMD AARCH64_HAVE_ISA (SIMD)
#define TARGET_SIMD (TARGET_BASE_SIMD && TARGET_NON_STREAMING)
#define TARGET_FLOAT AARCH64_HAVE_ISA (FP)
/* AARCH64_FL options necessary for system register implementation. */
/* Define AARCH64_FL aliases for architectural features which are protected
by -march flags in binutils but which receive no special treatment by GCC.
Such flags are inherited from the Binutils definition of system registers
and are mapped to the architecture in which the feature is implemented. */
#define AARCH64_FL_RAS AARCH64_FL_V8A
#define AARCH64_FL_LOR AARCH64_FL_V8_1A
#define AARCH64_FL_PAN AARCH64_FL_V8_1A
#define AARCH64_FL_AMU AARCH64_FL_V8_4A
#define AARCH64_FL_SCXTNUM AARCH64_FL_V8_5A
#define AARCH64_FL_ID_PFR2 AARCH64_FL_V8_5A
/* Armv8.9-A extension feature bits defined in Binutils but absent from GCC,
aliased to their base architecture. */
#define AARCH64_FL_AIE AARCH64_FL_V8_9A
#define AARCH64_FL_DEBUGv8p9 AARCH64_FL_V8_9A
#define AARCH64_FL_FGT2 AARCH64_FL_V8_9A
#define AARCH64_FL_ITE AARCH64_FL_V8_9A
#define AARCH64_FL_PFAR AARCH64_FL_V8_9A
#define AARCH64_FL_PMUv3_ICNTR AARCH64_FL_V8_9A
#define AARCH64_FL_PMUv3_SS AARCH64_FL_V8_9A
#define AARCH64_FL_PMUv3p9 AARCH64_FL_V8_9A
#define AARCH64_FL_RASv2 AARCH64_FL_V8_9A
#define AARCH64_FL_S1PIE AARCH64_FL_V8_9A
#define AARCH64_FL_S1POE AARCH64_FL_V8_9A
#define AARCH64_FL_S2PIE AARCH64_FL_V8_9A
#define AARCH64_FL_S2POE AARCH64_FL_V8_9A
#define AARCH64_FL_SCTLR2 AARCH64_FL_V8_9A
#define AARCH64_FL_SEBEP AARCH64_FL_V8_9A
#define AARCH64_FL_SPE_FDS AARCH64_FL_V8_9A
#define AARCH64_FL_TCR2 AARCH64_FL_V8_9A
#define TARGET_V8R AARCH64_HAVE_ISA (V8R)
#define TARGET_V9A AARCH64_HAVE_ISA (V9A)
/* SHA2 is an optional extension to AdvSIMD. */
#define TARGET_SHA2 AARCH64_HAVE_ISA (SHA2)
/* SHA3 is an optional extension to AdvSIMD. */
#define TARGET_SHA3 AARCH64_HAVE_ISA (SHA3)
/* AES is an optional extension to AdvSIMD. */
#define TARGET_AES AARCH64_HAVE_ISA (AES)
/* SM is an optional extension to AdvSIMD. */
#define TARGET_SM4 AARCH64_HAVE_ISA (SM4)
/* CRC instructions that can be enabled through +crc arch extension. */
#define TARGET_CRC32 AARCH64_HAVE_ISA (CRC)
/* Atomic instructions that can be enabled through the +lse extension. */
#define TARGET_LSE AARCH64_HAVE_ISA (LSE)
/* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension. */
#define TARGET_FP_F16INST AARCH64_HAVE_ISA (F16)
#define TARGET_SIMD_F16INST (TARGET_SIMD && TARGET_FP_F16INST)
/* FP16FML is an optional extension to AdvSIMD. */
#define TARGET_F16FML (TARGET_SIMD_F16INST && AARCH64_HAVE_ISA (F16FML))
/* Dot Product is an optional extension to AdvSIMD enabled through +dotprod.
*/
#define TARGET_DOTPROD AARCH64_HAVE_ISA (DOTPROD)
/* SVE instructions, enabled through +sve. */
#define TARGET_SVE AARCH64_HAVE_ISA (SVE)
/* SVE2 instructions, enabled through +sve2. */
#define TARGET_SVE2 AARCH64_HAVE_ISA (SVE2)
/* SVE2 AES instructions, enabled through +sve2-aes. */
#define TARGET_SVE2_AES (AARCH64_HAVE_ISA (SVE2_AES) && TARGET_NON_STREAMING)
/* SVE2 BITPERM instructions, enabled through +sve2-bitperm. */
#define TARGET_SVE2_BITPERM (AARCH64_HAVE_ISA (SVE2_BITPERM) \
&& TARGET_NON_STREAMING)
/* SVE2 SHA3 instructions, enabled through +sve2-sha3. */
#define TARGET_SVE2_SHA3 (AARCH64_HAVE_ISA (SVE2_SHA3) && TARGET_NON_STREAMING)
/* SVE2 SM4 instructions, enabled through +sve2-sm4. */
#define TARGET_SVE2_SM4 (AARCH64_HAVE_ISA (SVE2_SM4) && TARGET_NON_STREAMING)
/* SVE2p1 instructions, enabled through +sve2p1. */
#define TARGET_SVE2p1 AARCH64_HAVE_ISA (SVE2p1)
/* SME instructions, enabled through +sme. Note that this does not
imply anything about the state of PSTATE.SM; instructions that require
SME and streaming mode should use TARGET_STREAMING instead. */
#define TARGET_SME AARCH64_HAVE_ISA (SME)
/* The FEAT_SME_I16I64 extension to SME, enabled through +sme-i16i64. */
#define TARGET_SME_I16I64 AARCH64_HAVE_ISA (SME_I16I64)
/* The FEAT_SME_B16B16 extension to SME, enabled through +sme-b16b16. */
#define TARGET_STREAMING_SME_B16B16 \
(AARCH64_HAVE_ISA (SME_B16B16) && TARGET_STREAMING)
/* The FEAT_SME_F16F16 extension to SME, enabled through +sme-f16f16. */
#define TARGET_STREAMING_SME_F16F16 \
(AARCH64_HAVE_ISA (SME_F16F16) && TARGET_STREAMING)
/* The FEAT_SME_F64F64 extension to SME, enabled through +sme-f64f64. */
#define TARGET_SME_F64F64 AARCH64_HAVE_ISA (SME_F64F64)
/* SME2 instructions, enabled through +sme2. */
#define TARGET_SME2 AARCH64_HAVE_ISA (SME2)
/* Same with streaming mode enabled. */
#define TARGET_STREAMING_SME2 (TARGET_STREAMING && TARGET_SME2)
#define TARGET_STREAMING_SME2p1 (TARGET_STREAMING && AARCH64_HAVE_ISA (SME2p1))
#define TARGET_SME_B16B16 AARCH64_HAVE_ISA (SME_B16B16)
/* ARMv8.3-A features. */
#define TARGET_ARMV8_3 AARCH64_HAVE_ISA (V8_3A)
/* Javascript conversion instruction from Armv8.3-a. */
#define TARGET_JSCVT AARCH64_HAVE_ISA (JSCVT)
/* Armv8.3-a Complex number extension to AdvSIMD extensions. */
#define TARGET_COMPLEX AARCH64_HAVE_ISA (FCMA)
/* Floating-point rounding instructions from Armv8.5-a. */
#define TARGET_FRINT AARCH64_HAVE_ISA (FRINTTS)
/* TME instructions are enabled. */
#define TARGET_TME AARCH64_HAVE_ISA (TME)
/* Random number instructions from Armv8.5-a. */
#define TARGET_RNG AARCH64_HAVE_ISA (RNG)
/* Memory Tagging instructions optional to Armv8.5 enabled through +memtag. */
#define TARGET_MEMTAG AARCH64_HAVE_ISA (MEMTAG)
/* I8MM instructions are enabled through +i8mm. */
#define TARGET_I8MM AARCH64_HAVE_ISA (I8MM)
#define TARGET_SVE_I8MM (TARGET_SVE && TARGET_I8MM)
/* F32MM instructions are enabled through +f32mm. */
#define TARGET_SVE_F32MM AARCH64_HAVE_ISA (F32MM)
/* F64MM instructions are enabled through +f64mm. */
#define TARGET_SVE_F64MM AARCH64_HAVE_ISA (F64MM)
/* BF16 instructions are enabled through +bf16. */
#define TARGET_BF16_FP AARCH64_HAVE_ISA (BF16)
#define TARGET_BF16_SIMD (TARGET_BF16_FP && TARGET_SIMD)
#define TARGET_SVE_BF16 (TARGET_BF16_FP && TARGET_SVE)
/* PAUTH instructions are enabled through +pauth. */
#define TARGET_PAUTH AARCH64_HAVE_ISA (PAUTH)
/* BTI instructions exist from Armv8.5-a onwards. Their automatic use is
enabled through -mbranch-protection by using NOP-space instructions,
but this TARGET_ is used for defining BTI-related ACLE things. */
#define TARGET_BTI AARCH64_HAVE_ISA (V8_5A)
/* MOPS instructions are enabled through +mops. */
#define TARGET_MOPS AARCH64_HAVE_ISA (MOPS)
/* LS64 instructions are enabled through +ls64. */
#define TARGET_LS64 AARCH64_HAVE_ISA (LS64)
/* CSSC instructions are enabled through +cssc. */
#define TARGET_CSSC AARCH64_HAVE_ISA (CSSC)
+/* CB<cc> instructions are enabled through +cmpbr. */
+#define TARGET_CMPBR AARCH64_HAVE_ISA (CMPBR)
+
/* Make sure this is always defined so we don't have to check for ifdefs
but rather use normal ifs. */
#ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
#define TARGET_FIX_ERR_A53_835769_DEFAULT 0
#else
#undef TARGET_FIX_ERR_A53_835769_DEFAULT
#define TARGET_FIX_ERR_A53_835769_DEFAULT 1
#endif
/* SB instruction is enabled through +sb. */
#define TARGET_SB AARCH64_HAVE_ISA (SB)
/* RCPC loads from Armv8.3-a. */
#define TARGET_RCPC AARCH64_HAVE_ISA (RCPC)
/* The RCPC2 extensions from Armv8.4-a that allow immediate offsets to LDAPR
and sign-extending versions.*/
#define TARGET_RCPC2 AARCH64_HAVE_ISA (RCPC2)
/* RCPC3 (Release Consistency) extensions, optional from Armv8.2-a. */
#define TARGET_RCPC3 AARCH64_HAVE_ISA (RCPC3)
/* Apply the workaround for Cortex-A53 erratum 835769. */
#define TARGET_FIX_ERR_A53_835769 \
((aarch64_fix_a53_err835769 == 2) \
? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769)
/* Make sure this is always defined so we don't have to check for ifdefs
but rather use normal ifs. */
#ifndef TARGET_FIX_ERR_A53_843419_DEFAULT
#define TARGET_FIX_ERR_A53_843419_DEFAULT 0
#else
#undef TARGET_FIX_ERR_A53_843419_DEFAULT
#define TARGET_FIX_ERR_A53_843419_DEFAULT 1
#endif
/* Apply the workaround for Cortex-A53 erratum 843419. */
#define TARGET_FIX_ERR_A53_843419 \
((aarch64_fix_a53_err843419 == 2) \
? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419)
/* ARMv8.1-A Adv.SIMD support. */
#define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_HAVE_ISA (RDMA))
/* Armv9.4-A features. */
#define TARGET_ARMV9_4 AARCH64_HAVE_ISA (V9_4A)
/* 128-bit System Registers and Instructions from Armv9.4-a are enabled
through +d128. */
#define TARGET_D128 AARCH64_HAVE_ISA (D128)
/* Armv8.9-A/9.4-A Translation Hardening Extension system registers are
enabled through +the. */
#define TARGET_THE AARCH64_HAVE_ISA (THE)
/* Armv9.4-A Guarded Control Stack extension system registers are
enabled through +gcs. */
#define TARGET_GCS AARCH64_HAVE_ISA (GCS)
/* Floating Point Absolute Maximum/Minimum extension instructions are
enabled through +faminmax. */
#define TARGET_FAMINMAX AARCH64_HAVE_ISA (FAMINMAX)
/* Lookup table (LUTI) extension instructions are enabled through +lut. */
#define TARGET_LUT AARCH64_HAVE_ISA (LUT)
/* Prefer different predicate registers for the output of a predicated
operation over re-using an existing input predicate. */
#define TARGET_SVE_PRED_CLOBBER (TARGET_SVE \
&& (aarch64_tune_params.extra_tuning_flags \
& AARCH64_EXTRA_TUNE_AVOID_PRED_RMW))
/* fp8 instructions are enabled through +fp8. */
#define TARGET_FP8 AARCH64_HAVE_ISA (FP8)
/* See the comment above the tuning flag for details. */
#define TARGET_CHEAP_FPMR_WRITE \
(bool (aarch64_tune_params.extra_tuning_flags \
& AARCH64_EXTRA_TUNE_CHEAP_FPMR_WRITE))
/* Combinatorial tests. */
#define TARGET_SVE2_OR_SME2 \
((TARGET_SVE2 || TARGET_STREAMING) \
&& (TARGET_SME2 || TARGET_NON_STREAMING))
/* There's no need to check TARGET_SME for streaming or streaming-compatible
functions, since streaming mode itself implies SME. */
#define TARGET_SVE2p1_OR_SME (TARGET_SVE2p1 || TARGET_STREAMING)
#define TARGET_SVE2p1_OR_SME2 \
((TARGET_SVE2p1 || TARGET_STREAMING) \
&& (TARGET_SME2 || TARGET_NON_STREAMING))
#define TARGET_SSVE_B16B16 \
(AARCH64_HAVE_ISA (SVE_B16B16) && TARGET_SVE2_OR_SME2)
/* Some fp8 instructions require +fp8 and one of +sve2 or +sme2. */
#define TARGET_SSVE_FP8 (TARGET_FP8 \
&& (TARGET_SVE2 || TARGET_STREAMING) \
&& (TARGET_SME2 || TARGET_NON_STREAMING))
/* fp8 multiply-accumulate instructions are enabled through +fp8fma. */
#define TARGET_FP8FMA AARCH64_HAVE_ISA (FP8FMA)
/* SVE2 versions of fp8 multiply-accumulate instructions are enabled for
non-streaming mode by +fp8fma and for streaming mode by +ssve-fp8fma. */
#define TARGET_SSVE_FP8FMA \
(((TARGET_SVE2 && TARGET_FP8FMA) || TARGET_STREAMING) \
&& (AARCH64_HAVE_ISA (SSVE_FP8FMA) || TARGET_NON_STREAMING))
/* fp8 four way dot product enabled through +fp8dot4. */
#define TARGET_FP8DOT4 AARCH64_HAVE_ISA (FP8DOT4)
/* Streaming versions of fp8 four way dot product instructions are enabled
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 32bc45725de..3f05e5e0e34 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -22252,6 +22252,9 @@ Enable the FlagM2 flag conversion instructions.
Enable the Pointer Authentication Extension.
@item cssc
Enable the Common Short Sequence Compression instructions.
+@item cmpbr
+Enable the shorter compare and branch instructions, @code{cbb}, @code{cbh} and
+@code{cb}.
@item sme
Enable the Scalable Matrix Extension. This is only supported when SVE2 is also
enabled.
--
2.45.2
