Hehe, you are late a little bit, let rewrite this with riscv-ext.def
On Tue, May 13, 2025 at 11:56 AM Jiawei <jia...@iscas.ac.cn> wrote: > > The augmented hypervisor series extensions 'sha'[1] is a new profile-defined > extension series that captures the full set of features that are mandated to > be supported along with the 'H' extension. > > [1] > https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23s64-profile > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: New extensions. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/arch-55.c: New test. > > --- > gcc/common/config/riscv/riscv-common.cc | 17 +++++++++++++++++ > gcc/testsuite/gcc.target/riscv/arch-55.c | 9 +++++++++ > 2 files changed, 26 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/arch-55.c > > diff --git a/gcc/common/config/riscv/riscv-common.cc > b/gcc/common/config/riscv/riscv-common.cc > index d3240f79240..8a2e22a1d57 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -254,6 +254,15 @@ static const riscv_implied_info_t riscv_implied_info[] = > return false; > }}, > > + {"sha", "h"}, > + {"sha", "shcounterenw"}, > + {"sha", "shgatpa"}, > + {"sha", "shtvala"}, > + {"sha", "shvstvala"}, > + {"sha", "shvstvecd"}, > + {"sha", "shvsatpa"}, > + {"sha", "ssstateen"}, > + > {"smaia", "ssaia"}, > {"smstateen", "ssstateen"}, > {"smepmp", "zicsr"}, > @@ -451,6 +460,14 @@ static const struct riscv_ext_version > riscv_ext_version_table[] = > > {"sdtrig", ISA_SPEC_CLASS_NONE, 1, 0}, > > + {"sha", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"shcounterenw", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"shgatpa", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"shtvala", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"shvsatpa", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"shvstvala", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"shvstvecd", ISA_SPEC_CLASS_NONE, 1, 0}, > + > {"smaia", ISA_SPEC_CLASS_NONE, 1, 0}, > {"smepmp", ISA_SPEC_CLASS_NONE, 1, 0}, > {"smstateen", ISA_SPEC_CLASS_NONE, 1, 0}, > diff --git a/gcc/testsuite/gcc.target/riscv/arch-55.c > b/gcc/testsuite/gcc.target/riscv/arch-55.c > new file mode 100644 > index 00000000000..50461f33946 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/arch-55.c > @@ -0,0 +1,9 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64g_sha -mabi=lp64d" } */ > + > +void foo(){} > + > +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2" > +"_d2p2_h1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_sha1p0" > +"_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0" > +"_ssstateen1p0_a1p0\"" } } */ > -- > 2.43.0 >
