Seems like you don't really add new intrinsics for those two new extensions? Also our policy is only to add extensions when they are ratified.
I am happy to review the patch anyway, but just remind you we won't accept that until it is ratified :) On Mon, Apr 14, 2025 at 4:25 PM Dongyan Chen <chendong...@isrc.iscas.ac.cn> wrote: > > This patch add zvfbfa and zvfofp8min intrinsic[1]. > To enable GCC to recognize and process zvfbfa and zvfofp8min extensions > correctly at compile time. > > [1]https://github.com/aswaterman/riscv-misc/blob/e515758c24504cf3c16145bc763a76c59425ed1b/isa/zvfbfa.adoc > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: New intrinsic. > * config/riscv/riscv-vector-builtins.cc > (validate_instance_type_required_extensions): Add required_ext checking for > 'zvfbfa' and 'zvfofp8min'. > * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_OFP_8): New > bit value for OFP8. > (enum required_ext): Add required_ext declaration for 'zvfbfa' and > 'zvfofp8min'. > (required_ext_to_isa_name): Ditto. > (required_extensions_specified): Ditto. > (struct function_group_info): Add match case for 'zvfbfa' and > 'zvfofp8min'. > * config/riscv/riscv.opt: New mask for 'zvfbfa' and 'zvfofp8min'. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/arch-45.c: New test. > * gcc.target/riscv/arch-46.c: New test. > > --- > gcc/common/config/riscv/riscv-common.cc | 9 +++++++++ > gcc/config/riscv/riscv-vector-builtins.cc | 20 ++++++++++++++++++++ > gcc/config/riscv/riscv-vector-builtins.h | 15 +++++++++++++++ > gcc/config/riscv/riscv.opt | 6 ++++++ > gcc/testsuite/gcc.target/riscv/arch-45.c | 5 +++++ > gcc/testsuite/gcc.target/riscv/arch-46.c | 5 +++++ > 6 files changed, 60 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c > create mode 100644 gcc/testsuite/gcc.target/riscv/arch-46.c > > diff --git a/gcc/common/config/riscv/riscv-common.cc > b/gcc/common/config/riscv/riscv-common.cc > index b34409adf39c..7aaa9d92455b 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -193,12 +193,15 @@ static const riscv_implied_info_t riscv_implied_info[] = > > {"zfa", "f"}, > > + {"zvfbfa", "zve32f"}, > + {"zvfbfa", "zfbfmin"}, > {"zvfbfmin", "zve32f"}, > {"zvfbfwma", "zvfbfmin"}, > {"zvfbfwma", "zfbfmin"}, > {"zvfhmin", "zve32f"}, > {"zvfh", "zve32f"}, > {"zvfh", "zfhmin"}, > + {"zvfofp8min", "zve32f"}, > > {"zhinx", "zhinxmin"}, > {"zhinxmin", "zfinx"}, > @@ -383,10 +386,12 @@ static const struct riscv_ext_version > riscv_ext_version_table[] = > {"zfbfmin", ISA_SPEC_CLASS_NONE, 1, 0}, > {"zfh", ISA_SPEC_CLASS_NONE, 1, 0}, > {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"zvfbfa", ISA_SPEC_CLASS_NONE, 0, 1}, > {"zvfbfmin", ISA_SPEC_CLASS_NONE, 1, 0}, > {"zvfbfwma", ISA_SPEC_CLASS_NONE, 1, 0}, > {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, > {"zvfh", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"zvfofp8min",ISA_SPEC_CLASS_NONE, 0, 2}, > > {"zfa", ISA_SPEC_CLASS_NONE, 1, 0}, > > @@ -1676,10 +1681,12 @@ static const riscv_ext_flag_table_t > riscv_ext_flag_table[] = > RISCV_EXT_FLAG_ENTRY ("zve64x", x_riscv_vector_elen_flags, > MASK_VECTOR_ELEN_64), > RISCV_EXT_FLAG_ENTRY ("zve64f", x_riscv_vector_elen_flags, > MASK_VECTOR_ELEN_FP_32), > RISCV_EXT_FLAG_ENTRY ("zve64d", x_riscv_vector_elen_flags, > MASK_VECTOR_ELEN_FP_64), > + RISCV_EXT_FLAG_ENTRY ("zvfbfa", x_riscv_vector_elen_flags, > MASK_VECTOR_ELEN_BF_16), > RISCV_EXT_FLAG_ENTRY ("zvfbfmin", x_riscv_vector_elen_flags, > MASK_VECTOR_ELEN_BF_16), > RISCV_EXT_FLAG_ENTRY ("zvfbfwma", x_riscv_vector_elen_flags, > MASK_VECTOR_ELEN_BF_16), > RISCV_EXT_FLAG_ENTRY ("zvfhmin", x_riscv_vector_elen_flags, > MASK_VECTOR_ELEN_FP_16), > RISCV_EXT_FLAG_ENTRY ("zvfh", x_riscv_vector_elen_flags, > MASK_VECTOR_ELEN_FP_16), > + RISCV_EXT_FLAG_ENTRY ("zvfofp8min", x_riscv_vector_elen_flags, > MASK_VECTOR_ELEN_OFP_8), > > RISCV_EXT_FLAG_ENTRY ("zvbb", x_riscv_zvb_subext, MASK_ZVBB), > RISCV_EXT_FLAG_ENTRY ("zvbc", x_riscv_zvb_subext, MASK_ZVBC), > @@ -1714,10 +1721,12 @@ static const riscv_ext_flag_table_t > riscv_ext_flag_table[] = > RISCV_EXT_FLAG_ENTRY ("zfbfmin", x_riscv_zf_subext, MASK_ZFBFMIN), > RISCV_EXT_FLAG_ENTRY ("zfhmin", x_riscv_zf_subext, MASK_ZFHMIN), > RISCV_EXT_FLAG_ENTRY ("zfh", x_riscv_zf_subext, MASK_ZFH), > + RISCV_EXT_FLAG_ENTRY ("zvfbfa", x_riscv_zf_subext, MASK_ZVFBFA), > RISCV_EXT_FLAG_ENTRY ("zvfbfmin", x_riscv_zf_subext, MASK_ZVFBFMIN), > RISCV_EXT_FLAG_ENTRY ("zvfbfwma", x_riscv_zf_subext, MASK_ZVFBFWMA), > RISCV_EXT_FLAG_ENTRY ("zvfhmin", x_riscv_zf_subext, MASK_ZVFHMIN), > RISCV_EXT_FLAG_ENTRY ("zvfh", x_riscv_zf_subext, MASK_ZVFH), > + RISCV_EXT_FLAG_ENTRY ("zvfofp8min", x_riscv_zf_subext, MASK_ZVFOFP8MIN), > > RISCV_EXT_FLAG_ENTRY ("zfa", x_riscv_zfa_subext, MASK_ZFA), > > diff --git a/gcc/config/riscv/riscv-vector-builtins.cc > b/gcc/config/riscv/riscv-vector-builtins.cc > index 61dcdabbb403..290b342abc56 100644 > --- a/gcc/config/riscv/riscv-vector-builtins.cc > +++ b/gcc/config/riscv/riscv-vector-builtins.cc > @@ -4915,6 +4915,26 @@ validate_instance_type_required_extensions (const > rvv_type_info type, > { > uint64_t exts = type.required_extensions; > > + if ((exts & RVV_REQUIRE_ELEN_BF_16) > + && !TARGET_VECTOR_ELEN_BF_16_P (riscv_vector_elen_flags)) > + { > + error_at (EXPR_LOCATION (exp), > + "built-in function %qE requires the " > + "zvfbfa ISA extension", > + exp); > + return false; > + } > + > + if ((exts & RVV_REQUIRE_ELEN_OFP_8) > + && !TARGET_VECTOR_ELEN_OFP_8_P (riscv_vector_elen_flags)) > + { > + error_at (EXPR_LOCATION (exp), > + "built-in function %qE requires the " > + "zvfofp8min ISA extension", > + exp); > + return false; > + } > + > if ((exts & RVV_REQUIRE_ELEN_BF_16) > && !TARGET_VECTOR_ELEN_BF_16_P (riscv_vector_elen_flags)) > { > diff --git a/gcc/config/riscv/riscv-vector-builtins.h > b/gcc/config/riscv/riscv-vector-builtins.h > index 42ba90577079..f3ca912bf725 100644 > --- a/gcc/config/riscv/riscv-vector-builtins.h > +++ b/gcc/config/riscv/riscv-vector-builtins.h > @@ -110,6 +110,7 @@ static const unsigned int CP_WRITE_CSR = 1U << 5; > #define RVV_REQUIRE_MIN_VLEN_64 (1 << 5) /* Require TARGET_MIN_VLEN >= > 64. */ > #define RVV_REQUIRE_ELEN_FP_16 (1 << 6) /* Require FP ELEN >= 32. */ > #define RVV_REQUIRE_ELEN_BF_16 (1 << 7) /* Require BF16. */ > +#define RVV_REQUIRE_ELEN_OFP_8 (1 << 8) /* Require OFP8. */ > > /* Enumerates the required extensions. */ > enum required_ext > @@ -125,8 +126,10 @@ enum required_ext > ZVKSED_EXT, /* Crypto vector Zvksed sub-ext */ > ZVKSH_EXT, /* Crypto vector Zvksh sub-ext */ > XTHEADVECTOR_EXT, /* XTheadVector extension */ > + ZVFBFA_EXT, /* Zvfbfa extension */ > ZVFBFMIN_EXT, /* Zvfbfmin extension */ > ZVFBFWMA_EXT, /* Zvfbfwma extension */ > + ZVFOFP8MIN_EXT, /* Zvfofp8min extension */ > XSFVQMACCQOQ_EXT, /* XSFVQMACCQOQ extension */ > XSFVQMACCDOD_EXT, /* XSFVQMACCDOD extension */ > XSFVFNRCLIPXFQF_EXT, /* XSFVFNRCLIPXFQF extension */ > @@ -159,10 +162,14 @@ static inline const char * required_ext_to_isa_name > (enum required_ext required) > return "zvksh"; > case XTHEADVECTOR_EXT: > return "xtheadvector"; > + case ZVFBFA_EXT: > + return "zvfbfa"; > case ZVFBFMIN_EXT: > return "zvfbfmin"; > case ZVFBFWMA_EXT: > return "zvfbfwma"; > + case ZVFOFP8MIN_EXT: > + return "zvfofp8min"; > case XSFVQMACCQOQ_EXT: > return "xsfvqmaccqoq"; > case XSFVQMACCDOD_EXT: > @@ -202,10 +209,14 @@ static inline bool required_extensions_specified (enum > required_ext required) > return TARGET_ZVKSH; > case XTHEADVECTOR_EXT: > return TARGET_XTHEADVECTOR; > + case ZVFBFA_EXT: > + return TARGET_ZVFBFA; > case ZVFBFMIN_EXT: > return TARGET_ZVFBFMIN; > case ZVFBFWMA_EXT: > return TARGET_ZVFBFWMA; > + case ZVFOFP8MIN_EXT: > + return TARGET_ZVFOFP8MIN; > case XSFVQMACCQOQ_EXT: > return TARGET_XSFVQMACCQOQ; > case XSFVQMACCDOD_EXT: > @@ -349,10 +360,14 @@ struct function_group_info > return TARGET_ZVKSH; > case XTHEADVECTOR_EXT: > return TARGET_XTHEADVECTOR; > + case ZVFBFA_EXT: > + return TARGET_ZVFBFA; > case ZVFBFMIN_EXT: > return TARGET_ZVFBFMIN; > case ZVFBFWMA_EXT: > return TARGET_ZVFBFWMA; > + case ZVFOFP8MIN_EXT: > + return TARGET_ZVFOFP8MIN; > case XSFVQMACCQOQ_EXT: > return TARGET_XSFVQMACCQOQ; > case XSFVQMACCDOD_EXT: > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index 7515c8ea13dd..800c0776f357 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -334,6 +334,8 @@ Mask(VECTOR_ELEN_FP_16) Var(riscv_vector_elen_flags) > > Mask(VECTOR_ELEN_BF_16) Var(riscv_vector_elen_flags) > > +Mask(VECTOR_ELEN_OFP_8) Var(riscv_vector_elen_flags) > + > TargetVariable > int riscv_zvl_flags > > @@ -426,6 +428,8 @@ Mask(ZFHMIN) Var(riscv_zf_subext) > > Mask(ZFH) Var(riscv_zf_subext) > > +Mask(ZVFBFA) Var(riscv_zf_subext) > + > Mask(ZVFBFMIN) Var(riscv_zf_subext) > > Mask(ZVFBFWMA) Var(riscv_zf_subext) > @@ -434,6 +438,8 @@ Mask(ZVFHMIN) Var(riscv_zf_subext) > > Mask(ZVFH) Var(riscv_zf_subext) > > +Mask(ZVFOFP8MIN) Var(riscv_zf_subext) > + > TargetVariable > int riscv_zfa_subext > > diff --git a/gcc/testsuite/gcc.target/riscv/arch-45.c > b/gcc/testsuite/gcc.target/riscv/arch-45.c > new file mode 100644 > index 000000000000..e7f3d35ba332 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/arch-45.c > @@ -0,0 +1,5 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gc_zvfbfa -mabi=lp64" } */ > +int foo() > +{ > +} > diff --git a/gcc/testsuite/gcc.target/riscv/arch-46.c > b/gcc/testsuite/gcc.target/riscv/arch-46.c > new file mode 100644 > index 000000000000..797b2af011ba > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/arch-46.c > @@ -0,0 +1,5 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gc_zvfofp8min -mabi=lp64" } */ > +int foo() > +{ > +} > -- > 2.43.0 >
