Re: [PATCH v2 1/2] The following changes enable P8700 processor for RISCV and P8700 is a high-performance processor from MIPS by extending RISCV with custom instructions.

[Umesh Kalappa]

>>Thanks.  I added the new cpu/tune options to the documentation in
doc/invoke.texi.
Thank you for the same

>>Going forward make sure to create a git commit message as well as a
ChangeLog entry.
Sure and we make sure that ChangeLog details in the commit log .

Thank you again
~U

On Tue, May 20, 2025 at 11:26 PM Jeff Law <jeffreya...@gmail.com> wrote:

>
>
> On 5/19/25 1:02 AM, Umesh Kalappa wrote:
> > ---
> >   gcc/config/riscv/mips-p8700.md   | 139 +++++++++++++++++++++++++++++++
> >   gcc/config/riscv/riscv-cores.def |   5 ++
> >   gcc/config/riscv/riscv-opts.h    |   3 +-
> >   gcc/config/riscv/riscv.cc        |  22 +++++
> >   gcc/config/riscv/riscv.md        |   3 +-
> >   5 files changed, 170 insertions(+), 2 deletions(-)
> >   create mode 100644 gcc/config/riscv/mips-p8700.md
> Thanks.  I added the new cpu/tune options to the documentation in
> doc/invoke.texi.
>
> Going forward make sure to create a git commit message as well as a
> ChangeLog entry.  You can look in the git log to see examples of commit
> messages.  The ChangeLog entry should be part of the commit message as
> we use scripting to create the ChangeLog file from the git commit messages.
>
> Jeff
>
>