On Wed, 2025-06-04 at 17:56 +0800, Jiawei wrote:
> +RISCV_CORE("xiangshan-kunminghu",
> "rv64imafdcbvh_sdtrig_sha_shcounterenw_"
> +
> "shgatpa_shlcofideleg_shtvala_shvsatpa_shvstvala_shvstvecd_"
> +
> "smaia_smcsrind_smdbltrp_smmpm_smnpm_smrnmi_smstateen_"
> +
> "ssaia_ssccptr_sscofpmf_sscounterenw_sscsrind_ssdbltrp_"
> +
> "ssnpm_sspm_ssstateen_ssstrict_sstc_sstvala_sstvecd_"
> +
> "ssu64xl_supm_svade_svbare_svinval_svnapot_svpbmt_za64rs_"
> +
> "zacas_zawrs_zba_zbb_zbc_"zbkb_zbkc_zbkx_zbs_zcb_zcmop_"
~~~~~^~~~~~
This quote doesn't seem right.
> +
> "zfa_zfh_zfhmin_zic64b_zicbom_zicbop_zicboz_ziccif_"
> +
> "zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintpause_"
> +
> "zihpm_zimop_zkn_zknd_zkne_zknh_zksed_zksh_zkt_zvbb_zvfh_"
> + "zvfhmin_zvkt_zvl128b_zvl32b_zvl64b",
IIUC zvl128b implies zvl32b and zvl64b, then should we explicitly give
zvl32b and zvl64b here?
> + "xiangshan-kunminghu")
--
Xi Ruoyao <xry...@xry111.site>
School of Aerospace Science and Technology, Xidian University
