LGTM
On Fri, Jun 6, 2025 at 3:06 PM <pan2...@intel.com> wrote: > > From: Pan Li <pan2...@intel.com> > > This patch would like to introduce the combine of vec_dup + vdivu.vv into > vdivu.vx on the cost value of GR2VR. The late-combine will take place if > the cost of GR2VR is zero, or reject the combine if non-zero like 1, 15 > in test. There will be two cases for the combine: > > Case 0: > | ... > | vmv.v.x > | L1: > | vdivu.vv > | J L1 > | ... > > Case 1: > | ... > | L1: > | vmv.v.x > | vdivu.vv > | J L1 > | ... > > Both will be combined to below if the cost of GR2VR is zero. > | ... > | L1: > | vdivu.vx > | J L1 > | ... > > The below test suites are passed for this patch series. > * The rv64gcv fully regression test. > > Pan Li (4): > RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2VR cost > RISC-V: Add test for vec_duplicate + vdivu.vv combine case 0 with GR2VR > cost 0, 2 and 15 > RISC-V: Add test for vec_duplicate + vdivu.vv combine case 1 with GR2VR > cost 0, 1 and 2 > RISC-V: Reconcile the existing test for vdivu.vx combine > > gcc/config/riscv/riscv-v.cc | 1 + > gcc/config/riscv/riscv.cc | 1 + > gcc/config/riscv/vector-iterators.md | 2 +- > .../rvv/autovec/binop/vdiv-rv32gcv-nofm.c | 4 +- > .../riscv/rvv/autovec/binop/vdiv-rv32gcv.c | 4 +- > .../rvv/autovec/binop/vdiv-rv64gcv-nofm.c | 4 +- > .../riscv/rvv/autovec/binop/vdiv-rv64gcv.c | 4 +- > .../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-1-u8.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-2-u8.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-3-u8.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-4-u16.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-4-u32.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-4-u64.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-4-u8.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-5-u16.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-5-u32.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-5-u64.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-5-u8.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx-6-u8.c | 2 + > .../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 196 ++++++++++++++++++ > .../rvv/autovec/vx_vf/vx_vdiv-run-1-u16.c | 15 ++ > .../rvv/autovec/vx_vf/vx_vdiv-run-1-u32.c | 15 ++ > .../rvv/autovec/vx_vf/vx_vdiv-run-1-u64.c | 15 ++ > .../rvv/autovec/vx_vf/vx_vdiv-run-1-u8.c | 15 ++ > 36 files changed, 315 insertions(+), 9 deletions(-) > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u16.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u32.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u64.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u8.c > > -- > 2.43.0 >
