[committed] RISC-V: Add -fno-pie flags to testcases

[Kito Cheng]

PIE may cause some code gen difference in the testcases, that will cause
problem when we configure toolchain with `--enable-default-pie`.

So adding -fno-pie flags to the testcases to avoid this issue.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/jump-table-large-code-model.c: Adding
        -fno-pie.
        * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Ditto.
        * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto.
        * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto.
        * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c: Ditto.
---
 gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c    | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c      | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c 
b/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c
index 1ee7f6c07d3..ab97b0fc0bb 100644
--- a/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c
+++ b/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64 -mcmodel=large" } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mcmodel=large -fno-pie" } */
 
 int foo(int x, int y)
 {
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
index 667f457d658..fab8e79fe72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh 
-mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh 
-mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie" 
} */
 
 #include "vadd-template.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
index 1d8a19ce0b2..80bdb683ad0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh 
-mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh 
-mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie" 
} */
 
 #include "vadd-template.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
index 1b6d50ed3bc..28b923599ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh 
-mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh 
-mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie" 
} */
 
 #include "vsub-template.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
index 0b22e9ad290..b0489493b04 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh 
-mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh 
-mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie" 
} */
 
 #include "vsub-template.h"
 
-- 
2.34.1