On 6/23/25 3:56 PM, Peter Bergner wrote:
On 6/20/25 10:38 PM, Jeff Law wrote:
+;; REG or REG+D where D fits in a simm12 and has the low 4 bits
+;; off. The REG+D form can be reloaded into a temporary if needed
+;; after FP elimination if that exposes an invalid offset.
+(define_predicate "prefetch_operand"
I think you mean 5 bits and not 4 bits, given your comments above and
the code using 0x1f, so testing the low 5 bits are zero.
I did mean 5 bits. It started at 4, then I realized I misread the docs
and updated the mask without updating the comment. Fixing in the
obvious way.
Thanks,
Jeff
