Hi Jeff,
> Just a nit. In several places you need to replace
> "UPPERCAE_NAME" with "UPPERCASE_NAME".
Fixed. Thanks for your review.
This is a patch series for Andes vender extension of RISC-V.
These patches are tested by riscv-gnu-toolchain gcc/g++ testsuite. And the
report is the same as without these patches.
========= Summary of gcc testsuite =========
| # of unexpected case / # of unique unexpected
case
| gcc | g++ | gfortran |
rv64gc/ lp64d/ medlow | 26 / 13 | 14 / 6 | - |
This patch add basic support for the following XAndes ISA extensions:
XANDESPERF
XANDESBFHCVT
XANDESVBFHCVT
XANDESVSINTLOAD
XANDESVPACKFPH
XANDESVDOT
gcc/ChangeLog:
* config/riscv/riscv-ext.def: Include riscv-ext-andes.def.
* config/riscv/riscv-ext.opt (riscv_xandes_subext): New variable.
(XANDESPERF) : New mask.
(XANDESBFHCVT): Ditto.
(XANDESVBFHCVT): Ditto.
(XANDESVSINTLOAD): Ditto.
(XANDESVPACKFPH): Ditto.
(XANDESVDOT): Ditto.
* config/riscv/t-riscv: Add riscv-ext-andes.def.
* doc/riscv-ext.texi: Regenerated.
* config/riscv/riscv-ext-andes.def: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xandes-predef-1.c: New test.
* gcc.target/riscv/xandes-predef-2.c: New test.
* gcc.target/riscv/xandes-predef-3.c: New test.
* gcc.target/riscv/xandes-predef-4.c: New test.
* gcc.target/riscv/xandes-predef-5.c: New test.
* gcc.target/riscv/xandes-predef-6.c: New test.
From 8643c4f10187b7ddd166bde3626330467146ac5c Mon Sep 17 00:00:00 2001
From: Kuan-Lin Chen <rufus@andestech.com>
Date: Mon, 31 Mar 2025 15:27:41 +0800
Subject: [PATCH 1/7] RISC-V: Add basic XAndes vendor extension support.
This patch add basic support for the following XAndes ISA extensions:
XANDESPERF
XANDESBFHCVT
XANDESVBFHCVT
XANDESVSINTLOAD
XANDESVPACKFPH
XANDESVDOT
gcc/ChangeLog:
* config/riscv/riscv-ext.def: Include riscv-ext-andes.def.
* config/riscv/riscv-ext.opt (riscv_xandes_subext): New variable.
(XANDESPERF) : New mask.
(XANDESBFHCVT): Ditto.
(XANDESVBFHCVT): Ditto.
(XANDESVSINTLOAD): Ditto.
(XANDESVPACKFPH): Ditto.
(XANDESVDOT): Ditto.
* config/riscv/t-riscv: Add riscv-ext-andes.def.
* doc/riscv-ext.texi: Regenerated.
* config/riscv/riscv-ext-andes.def: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xandes-predef-1.c: New test.
* gcc.target/riscv/xandes-predef-2.c: New test.
* gcc.target/riscv/xandes-predef-3.c: New test.
* gcc.target/riscv/xandes-predef-4.c: New test.
* gcc.target/riscv/xandes-predef-5.c: New test.
* gcc.target/riscv/xandes-predef-6.c: New test.
Co-author: Lino Hsing-Yu Peng (linopeng@andestech.com),
Kai Kai-Yi Weng (kaiweng@andestech.com).
---
gcc/config/riscv/riscv-ext-andes.def | 100 ++++++++++++++++++
gcc/config/riscv/riscv-ext.def | 1 +
gcc/config/riscv/riscv-ext.opt | 15 +++
gcc/config/riscv/t-riscv | 3 +-
gcc/doc/riscv-ext.texi | 24 +++++
.../gcc.target/riscv/xandes-predef-1.c | 14 +++
.../gcc.target/riscv/xandes-predef-2.c | 14 +++
.../gcc.target/riscv/xandes-predef-3.c | 14 +++
.../gcc.target/riscv/xandes-predef-4.c | 14 +++
.../gcc.target/riscv/xandes-predef-5.c | 14 +++
.../gcc.target/riscv/xandes-predef-6.c | 14 +++
11 files changed, 226 insertions(+), 1 deletion(-)
create mode 100644 gcc/config/riscv/riscv-ext-andes.def
create mode 100644 gcc/testsuite/gcc.target/riscv/xandes-predef-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xandes-predef-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xandes-predef-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xandes-predef-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xandes-predef-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xandes-predef-6.c
diff --git a/gcc/config/riscv/riscv-ext-andes.def b/gcc/config/riscv/riscv-ext-andes.def
new file mode 100644
index 000000000000..4226e3ed86fe
--- /dev/null
+++ b/gcc/config/riscv/riscv-ext-andes.def
@@ -0,0 +1,100 @@
+/* Andes extension definition file for RISC-V.
+ Copyright (C) 2025 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>.
+
+Please run `make riscv-regen` in build folder to make sure updated anything.
+
+Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */
+
+DEFINE_RISCV_EXT(
+ /* NAME */ xandesperf,
+ /* UPPERCASE_NAME */ XANDESPERF,
+ /* FULL_NAME */ "Andes performace extension",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({}),
+ /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+ /* FLAG_GROUP */ xandes,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+ /* NAME */ xandesbfhcvt,
+ /* UPPERCASE_NAME */ XANDESBFHCVT,
+ /* FULL_NAME */ "Andes bfloat16 conversion extension",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({}),
+ /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+ /* FLAG_GROUP */ xandes,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+ /* NAME */ xandesvbfhcvt,
+ /* UPPERCASE_NAME */ XANDESVBFHCVT,
+ /* FULL_NAME */ "Andes vector bfloat16 conversion extension",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({}),
+ /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+ /* FLAG_GROUP */ xandes,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+ /* NAME */ xandesvsintload,
+ /* UPPERCASE_NAME */ XANDESVSINTLOAD,
+ /* FULL_NAME */ "Andes vector INT4 load extension",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({}),
+ /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+ /* FLAG_GROUP */ xandes,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+ /* NAME */ xandesvpackfph,
+ /* UPPERCASE_NAME */ XANDESVPACKFPH,
+ /* FULL_NAME */ "Andes vector packed FP16 extension",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({}),
+ /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+ /* FLAG_GROUP */ xandes,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+ /* NAME */ xandesvdot,
+ /* UPPERCASE_NAME */ XANDESVDOT,
+ /* FULL_NAME */ "Andes vector dot product extension",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({}),
+ /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+ /* FLAG_GROUP */ xandes,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 816acaa34f4a..92cc07a0752a 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -2082,3 +2082,4 @@ DEFINE_RISCV_EXT(
#include "riscv-ext-sifive.def"
#include "riscv-ext-thead.def"
#include "riscv-ext-ventana.def"
+#include "riscv-ext-andes.def"
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 9f8c5451d497..01d480d3b6a7 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -43,6 +43,9 @@ int riscv_su_subext
TargetVariable
int riscv_sv_subext
+TargetVariable
+int riscv_xandes_subext
+
TargetVariable
int riscv_xcv_subext
@@ -397,6 +400,18 @@ Mask(SVADE) Var(riscv_sv_subext)
Mask(SVBARE) Var(riscv_sv_subext)
+Mask(XANDESPERF) Var(riscv_xandes_subext)
+
+Mask(XANDESBFHCVT) Var(riscv_xandes_subext)
+
+Mask(XANDESVBFHCVT) Var(riscv_xandes_subext)
+
+Mask(XANDESVSINTLOAD) Var(riscv_xandes_subext)
+
+Mask(XANDESVPACKFPH) Var(riscv_xandes_subext)
+
+Mask(XANDESVDOT) Var(riscv_xandes_subext)
+
Mask(XCVALU) Var(riscv_xcv_subext)
Mask(XCVBI) Var(riscv_xcv_subext)
diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index 32092d856878..0309c84e81d4 100644
--- a/gcc/config/riscv/t-riscv
+++ b/gcc/config/riscv/t-riscv
@@ -194,7 +194,8 @@ RISCV_EXT_DEFS = \
$(srcdir)/config/riscv/riscv-ext.def \
$(srcdir)/config/riscv/riscv-ext-sifive.def \
$(srcdir)/config/riscv/riscv-ext-thead.def \
- $(srcdir)/config/riscv/riscv-ext-ventana.def
+ $(srcdir)/config/riscv/riscv-ext-ventana.def \
+ $(srcdir)/config/riscv/riscv-ext-andes.def
$(srcdir)/config/riscv/riscv-ext.opt: $(RISCV_EXT_DEFS)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index c3ed1bfb5936..4cd879d48491 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -714,4 +714,28 @@
@tab 1.0
@tab Ventana integer conditional operations extension
+@item xandesperf
+@tab 5.0
+@tab Andes performace extension
+
+@item xandesbfhcvt
+@tab 5.0
+@tab Andes bfloat16 conversion extension
+
+@item xandesvbfhcvt
+@tab 5.0
+@tab Andes vector bfloat16 conversion extension
+
+@item xandesvsintload
+@tab 5.0
+@tab Andes vector INT4 load extension
+
+@item xandesvpackfph
+@tab 5.0
+@tab Andes vector packed FP16 extension
+
+@item xandesvdot
+@tab 5.0
+@tab Andes vector dot product extension
+
@end multitable
diff --git a/gcc/testsuite/gcc.target/riscv/xandes-predef-1.c b/gcc/testsuite/gcc.target/riscv/xandes-predef-1.c
new file mode 100644
index 000000000000..24391312fa47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xandes-predef-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xandesperf -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xandesperf)
+#error "__riscv_xandesperf"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/xandes-predef-2.c b/gcc/testsuite/gcc.target/riscv/xandes-predef-2.c
new file mode 100644
index 000000000000..0e2e2d6260c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xandes-predef-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xandesbfhcvt -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xandesbfhcvt)
+#error "__riscv_xandesbfhcvt"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/xandes-predef-3.c b/gcc/testsuite/gcc.target/riscv/xandes-predef-3.c
new file mode 100644
index 000000000000..62f4c286b4bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xandes-predef-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xandesvbfhcvt -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xandesvbfhcvt)
+#error "__riscv_xandesvbfhcvt"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/xandes-predef-4.c b/gcc/testsuite/gcc.target/riscv/xandes-predef-4.c
new file mode 100644
index 000000000000..3074b5a2a9b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xandes-predef-4.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xandesvsintload -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xandesvsintload)
+#error "__riscv_xandesvsintload"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/xandes-predef-5.c b/gcc/testsuite/gcc.target/riscv/xandes-predef-5.c
new file mode 100644
index 000000000000..de5fe31373a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xandes-predef-5.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xandesvpackfph -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xandesvpackfph)
+#error "__riscv_xandesvpackfph"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/xandes-predef-6.c b/gcc/testsuite/gcc.target/riscv/xandes-predef-6.c
new file mode 100644
index 000000000000..728d54106c78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xandes-predef-6.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xandesvdot -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xandesvdot)
+#error "__riscv_xandesvdot"
+#endif
+
+ return 0;
+}
--
2.34.1
