Hi Kito, >>* +(define_predicate "extract_loc_imm_si"*
> Rename it to unsigned_5_bit_integer_operand
>>* + (and (match_code "const_int")
*>>* + (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
*>>* +*
>>* +(define_predicate "extract_loc_imm_di"*
> Rename it to unsigned_6_bit_integer_operand
>>* + (and (match_code "const_int") *>>* + (match_test "IN_RANGE (INTVAL
(op), 0, 63)")))*
All fixed as you mentioned. But I use "const_int6_operand" that already
defined to substitute *"extract_loc_imm_di".*
And Define "const_int5_operand" to substitute "*extract_loc_imm_si".*
Hi Jeff,
> It doesn't look like the conditional branch patterns support out of
> range targets. Or is there something I'm missing?
> Long branch handling isn't terribly hard. For most cases it'll end up
> generating assembly like this (from the "branch" pattern in riscv.md:
>* {
*>* if (get_attr_length (insn) == 12)
*>* return "b%r1\t%2,%z3,1f; jump\t%l0,ra; 1:";
*> >* return "b%C1\t%2,%z3,%l0";
*>* }*
> Closely related, I think your "length" attribute is wrong and needs
> updating. Length is usually computed by generic code, is that not
> working in your case?
Add long branch handling and remove "length" on
"*nds_branch_imms7<mode>" and "*nds_branch_on_bit<X:mode>"
> One of your cost cases sets *total = 0. That seems quite unexpected.
> Is that actually correct? I would have expected COSTS_N_INSNS (1).
This is for "*nds_branch_on_bit<X:mode>", we expect to lower the
"ZERO_EXTRACT" cost for the combine phase to generate
the pattern easierly.
> For the riscv.md define_insn_and_splits that you changed, changing the
> condition seems correct. But I don't think you need to change the split
> conditional. When the split condition starts with "&&" it'll use the
> main condition && the split condition.
Fixed. Thanks for your remind. I don't know the minor difference before.
Thanks to both of you.
This patch adds support for the XAndesperf ISA extension.
The 32-bit AndeStar V5 extension includes branch instructions,
load effective address instructions, and string processing
instructions for performance improvement.
New INSN patterns are added into the new file andes.md
as a seprated vender extension.
gcc/ChangeLog:
* config/riscv/constraints.md (Ou07): New constraint.
(ads_Bext): New constraint.
* config/riscv/iterators.md (ANYLE32): New iterator.
(sizen): New iterator.
(sh_limit): New iterator.
(sh_bit): New iterator.
* config/riscv/predicates.md (ads_branch_bbcs_operand): New predicate.
(ads_branch_bimm_operand): New predicate.
(ads_imm_extract_operand): New predicate.
(ads_extract_size_imm_si): New predicate.
(ads_extract_size_imm_di): New predicate.
(const_int5_operand): New predicate.
* config/riscv/riscv-builtins.cc:
Add new AVAIL andesperf32 and andesperf64.
Add new define RISCV_ATYPE_ULONG and RISCV_ATYPE_LONG.
* config/riscv/riscv-ftypes.def: New DEF_RISCV_FTYPE.
* config/riscv/riscv.cc
(riscv_extend_cost): Cost for pattern 'bfo'.
(riscv_rtx_costs): Cost for XAndesperf extension.
* config/riscv/riscv.md: Add support for XAndesperf to patterns
zero_extendsidi2_internal, zero_extendhi2, extendsidi2_internal,
extend<SHORT:mode><SUPERQI:mode>2, <any_extract:optab><GPR:mode>3
and branch_on_bit.
* config/riscv/vector-iterators.md
(sz): Add sign_extract and zero_extract.
* config/riscv/andes.def: New file for vender Andes.
* config/riscv/andes.md: New file for vender Andes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xandesperf-1.c: New test.
* gcc.target/riscv/xandesperf-10.c: New test.
* gcc.target/riscv/xandesperf-2.c: New test.
* gcc.target/riscv/xandesperf-3.c: New test.
* gcc.target/riscv/xandesperf-4.c: New test.
* gcc.target/riscv/xandesperf-5.c: New test.
* gcc.target/riscv/xandesperf-6.c: New test.
* gcc.target/riscv/xandesperf-7.c: New test.
* gcc.target/riscv/xandesperf-8.c: New test.
* gcc.target/riscv/xandesperf-9.c: New test.
0002-RISC-V-Add-support-for-the-XAndesperf-ISA-extension.patch
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