[PATCH v1] RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg_ceil

[pan2 . li]

From: Pan Li <pan2...@intel.com>

According to the semantics of the avg_floor and avg_ceil as below:

floor: op0 = (narrow) (((wide) op1 + (wide) op2) >> 1);
ceil:  op0 = (narrow) (((wide) op1 + (wide) op2 + 1) >> 1);

Aka we have (const_int 1) as the op2 of the ashiftrt but seems missed.
Thus, add it back to align the definition.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/ChangeLog:

        * config/riscv/autovec.md: Add (const_int 1) as the op2 of
        ashiftrt.

Signed-off-by: Pan Li <pan2...@intel.com>
---
 gcc/config/riscv/autovec.md | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index da5d0e34d0a..1fff8ac2fc4 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2489,7 +2489,8 @@ (define_expand "avg<v_double_trunc>3_floor"
       (sign_extend:VWEXTI
        (match_operand:<V_DOUBLE_TRUNC> 1 "register_operand"))
       (sign_extend:VWEXTI
-       (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))))))]
+       (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand")))
+     (const_int 1))))]
   "TARGET_VECTOR"
   {
     insn_code icode = code_for_pred (UNSPEC_VAADD, <V_DOUBLE_TRUNC>mode);
@@ -2522,7 +2523,8 @@ (define_expand "avg<v_double_trunc>3_ceil"
        (match_operand:<V_DOUBLE_TRUNC> 1 "register_operand"))
        (sign_extend:VWEXTI
        (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand")))
-      (const_int 1)))))]
+      (const_int 1))
+     (const_int 1))))]
   "TARGET_VECTOR"
   {
     insn_code icode = code_for_pred (UNSPEC_VAADD, <V_DOUBLE_TRUNC>mode);
-- 
2.43.0