Please find: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release These instructions are from "3.1.26. NDS.FFB" to "3.1.29. NDS.FLMISM" in AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf. Thanks.
Jeff Law <jeffreya...@gmail.com> 於 2025年7月30日 週三 下午11:22寫道： > > > > On 7/29/25 7:41 PM, KuanLin Chen wrote: > > > > >>> > >>> + > >>> +;; > >>> +;; .................... > >>> +;; > >>> +;; String Extension > >>> +;; > >>> +;; .................... > >>> +;; > >>> + > >>> +(define_insn "riscv_nds_ffb<mode>" > >>> + [(set (match_operand:GPR 0 "register_operand" "=r") > >>> + (unspec:GPR [(match_operand:GPR 1 "reg_or_0_operand" "rJ") > >>> + (match_operand:GPR 2 "nonmemory_operand" "rJ")] > >>> UNSPEC_NDS_FFB))] > >>> + "" > >>> + "nds.ffb\t%0, %z1, %z2" > >>> + [(set_attr "mode" "<MODE>") > >>> + (set_attr "type" "arith")]) > >> > >>> + > >>> +(define_insn "riscv_nds_ffzmism<mode>" > >>> + [(set (match_operand:GPR 0 "register_operand" "=r") > >>> + (unspec:GPR [(match_operand:GPR 1 "reg_or_0_operand" "rJ") > >>> + (match_operand:GPR 2 "reg_or_0_operand" "rJ")] > >>> UNSPEC_NDS_FFZMISM))] > >>> + "" > >>> + "nds.ffzmism\t%0, %z1, %z2" > >>> + [(set_attr "mode" "<MODE>") > >>> + (set_attr "type" "arith")]) > >>> + > >>> +(define_insn "riscv_nds_ffmism<mode>" > >>> + [(set (match_operand:GPR 0 "register_operand" "=r") > >>> + (unspec:GPR [(match_operand:GPR 1 "reg_or_0_operand" "rJ") > >>> + (match_operand:GPR 2 "reg_or_0_operand" "rJ")] > >>> UNSPEC_NDS_FFMISM))] > >>> + "" > >>> + "nds.ffmism\t%0, %z1, %z2" > >>> + [(set_attr "mode" "<MODE>") > >>> + (set_attr "type" "arith")]) > >>> + > >>> +(define_insn "riscv_nds_flmism<mode>" > >>> + [(set (match_operand:GPR 0 "register_operand" "=r") > >>> + (unspec:GPR [(match_operand:GPR 1 "reg_or_0_operand" "rJ") > >>> + (match_operand:GPR 2 "reg_or_0_operand" "rJ")] > >>> UNSPEC_NDS_FLMISM))] > >>> + "" > >>> + "nds.flmism\t%0, %z1, %z2" > >>> + [(set_attr "mode" "<MODE>") > >>> + (set_attr "type" "arith")]) > >> What are the semantics of these UNSPECs? Do they match existing RTL > >> code, and if so wouldn't it be better to use the existing RTL codes? > > > > These UNPSECs are for string processing instructions and we only > > provide intrinsic functions for users. > > There seems no existing RTL codes about string operations. > It'd still be useful to know the semantics. Even if we don't have a > mapping to RTL now, understanding what kinds of target specific > operations folks are wiring up via UNSPECs can help guide adding new RTL > codes. > > Feel free to just point me at an ISA specification if that's easier than > describing them. I didn't see one after some quick google searching. > > Thanks, > Jeff
