> On 29 Jul 2025, at 18:41, Richard Sandiford <richard.sandif...@arm.com> wrote:
> 
> This patch continues the work of making ACLE intrinsics use VNx16BI
> for svbool_t results.  It deals with the svmatch* and svnmatch*
> intrinsics.
> 

Ok.
Thanks,
Kyrill

> gcc/
> * config/aarch64/aarch64-sve2.md (@aarch64_pred_<sve_int_op><mode>):
> Split SVE2_MATCH pattern into a VNx16QI_ONLY define_ins and a
> VNx8HI_ONLY define_expand.  Use a VNx16BI destination for the latter.
> (*aarch64_pred_<sve_int_op><mode>): New SVE2_MATCH pattern for
> VNx8HI_ONLY.
> (*aarch64_pred_<sve_int_op><mode>_cc): Likewise.
> 
> gcc/testsuite/
> * gcc.target/aarch64/sve2/acle/general/match_4.c: New test.
> * gcc.target/aarch64/sve2/acle/general/nmatch_1.c: Likewise.
> ---
> gcc/config/aarch64/aarch64-sve2.md            | 88 ++++++++++++++++++-
> .../aarch64/sve2/acle/general/match_4.c       | 30 +++++++
> .../aarch64/sve2/acle/general/nmatch_1.c      | 30 +++++++
> 3 files changed, 146 insertions(+), 2 deletions(-)
> create mode 100644 
> gcc/testsuite/gcc.target/aarch64/sve2/acle/general/match_4.c
> create mode 100644 
> gcc/testsuite/gcc.target/aarch64/sve2/acle/general/nmatch_1.c
> 
> diff --git a/gcc/config/aarch64/aarch64-sve2.md 
> b/gcc/config/aarch64/aarch64-sve2.md
> index 31bdd85ddb2..a4c3257d087 100644
> --- a/gcc/config/aarch64/aarch64-sve2.md
> +++ b/gcc/config/aarch64/aarch64-sve2.md
> @@ -4068,8 +4068,8 @@ (define_insn "@aarch64_pred_<sve_int_op><mode>"
>  [(match_operand:<VPRED> 1 "register_operand")
>   (match_operand:SI 2 "aarch64_sve_ptrue_flag")
>   (unspec:<VPRED>
> -     [(match_operand:SVE_FULL_BHI 3 "register_operand")
> -      (match_operand:SVE_FULL_BHI 4 "register_operand")]
> +     [(match_operand:VNx16QI_ONLY 3 "register_operand")
> +      (match_operand:VNx16QI_ONLY 4 "register_operand")]
>     SVE2_MATCH)]
>  UNSPEC_PRED_Z))
>    (clobber (reg:CC_NZC CC_REGNUM))]
> @@ -4081,6 +4081,51 @@ (define_insn "@aarch64_pred_<sve_int_op><mode>"
>   }
> )
> 
> +(define_expand "@aarch64_pred_<sve_int_op><mode>"
> +  [(parallel
> +     [(set (match_operand:VNx16BI 0 "register_operand")
> +   (and:VNx16BI
> +     (subreg:VNx16BI
> +       (unspec:<VPRED>
> + [(match_operand:<VPRED> 1 "register_operand")
> +  (match_operand:SI 2 "aarch64_sve_ptrue_flag")
> +  (unspec:<VPRED>
> +    [(match_operand:VNx8HI_ONLY 3 "register_operand")
> +     (match_operand:VNx8HI_ONLY 4 "register_operand")]
> +    SVE2_MATCH)]
> + UNSPEC_PRED_Z)
> +       0)
> +     (match_dup 5)))
> +      (clobber (reg:CC_NZC CC_REGNUM))])]
> +  "TARGET_SVE2 && TARGET_NON_STREAMING"
> +  {
> +    operands[5] = aarch64_ptrue_all (GET_MODE_UNIT_SIZE (<MODE>mode));
> +  }
> +)
> +
> +(define_insn "*aarch64_pred_<sve_int_op><mode>"
> +  [(set (match_operand:VNx16BI 0 "register_operand")
> + (and:VNx16BI
> +  (subreg:VNx16BI
> +    (unspec:<VPRED>
> +      [(match_operand:<VPRED> 1 "register_operand")
> +       (match_operand:SI 2 "aarch64_sve_ptrue_flag")
> +       (unspec:<VPRED>
> + [(match_operand:VNx8HI_ONLY 3 "register_operand")
> +  (match_operand:VNx8HI_ONLY 4 "register_operand")]
> + SVE2_MATCH)]
> +      UNSPEC_PRED_Z)
> +    0)
> +  (match_operand:<VPRED> 5 "aarch64_ptrue_all_operand")))
> +   (clobber (reg:CC_NZC CC_REGNUM))]
> +  "TARGET_SVE2 && TARGET_NON_STREAMING"
> +  {@ [ cons: =0, 1  , 3, 4; attrs: pred_clobber ]
> +     [ &Upa    , Upl, w, w; yes                 ] <sve_int_op>\t%0.<Vetype>, 
> %1/z, %3.<Vetype>, %4.<Vetype>
> +     [ ?Upl    , 0  , w, w; yes                 ] ^
> +     [ Upa     , Upl, w, w; no                  ] ^
> +  }
> +)
> +
> ;; Predicated string matching in which both the flag and predicate results
> ;; are interesting.
> (define_insn_and_rewrite "*aarch64_pred_<sve_int_op><mode>_cc"
> @@ -4118,6 +4163,45 @@ (define_insn_and_rewrite 
> "*aarch64_pred_<sve_int_op><mode>_cc"
>   }
> )
> 
> +(define_insn_and_rewrite "*aarch64_pred_<sve_int_op><mode>_cc"
> +  [(set (reg:CC_NZC CC_REGNUM)
> + (unspec:CC_NZC
> +  [(match_operand:VNx16BI 1 "register_operand" "Upl")
> +   (match_operand 4)
> +   (match_operand:SI 5 "aarch64_sve_ptrue_flag")
> +   (unspec:<VPRED>
> +     [(match_operand 6)
> +      (match_operand:SI 7 "aarch64_sve_ptrue_flag")
> +      (unspec:<VPRED>
> + [(match_operand:VNx8HI_ONLY 2 "register_operand" "w")
> + (match_operand:VNx8HI_ONLY 3 "register_operand" "w")]
> + SVE2_MATCH)]
> +     UNSPEC_PRED_Z)]
> +  UNSPEC_PTEST))
> +   (set (match_operand:VNx16BI 0 "register_operand" "=Upa")
> + (and:VNx16BI
> +  (subreg:VNx16BI
> +    (unspec:<VPRED>
> +      [(match_dup 6)
> +       (match_dup 7)
> +       (unspec:<VPRED>
> + [(match_dup 2)
> +  (match_dup 3)]
> + SVE2_MATCH)]
> +      UNSPEC_PRED_Z)
> +    0)
> +  (match_operand:<VPRED> 8 "aarch64_ptrue_all_operand")))]
> +  "TARGET_SVE2
> +   && TARGET_NON_STREAMING
> +   && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])"
> +  "<sve_int_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>"
> +  "&& !rtx_equal_p (operands[4], operands[6])"
> +  {
> +    operands[6] = copy_rtx (operands[4]);
> +    operands[7] = operands[5];
> +  }
> +)
> +
> ;; Predicated string matching in which only the flags result is interesting.
> (define_insn_and_rewrite "*aarch64_pred_<sve_int_op><mode>_ptest"
>   [(set (reg:CC_NZC CC_REGNUM)
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/match_4.c 
> b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/match_4.c
> new file mode 100644
> index 00000000000..57f625b2f64
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/match_4.c
> @@ -0,0 +1,30 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +
> +#include <arm_sve.h>
> +
> +svbool_t
> +test1 (svbool_t pg, svint16_t x, svint16_t y)
> +{
> +  return svand_z (svptrue_b8 (),
> +  svmatch (pg, x, y),
> +  svptrue_b16 ());
> +}
> +
> +svbool_t
> +test2 (svbool_t pg, svint16_t x, svint16_t y)
> +{
> +  return svand_z (svptrue_b16 (),
> +  svmatch (pg, x, y),
> +  svptrue_b8 ());
> +}
> +
> +svbool_t
> +test3 (svbool_t pg, svint16_t x, svint16_t y)
> +{
> +  return svand_z (svptrue_b16 (),
> +  svmatch (pg, x, y),
> +  svptrue_b16 ());
> +}
> +
> +/* { dg-final { scan-assembler-not {\tand\t} } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/nmatch_1.c 
> b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/nmatch_1.c
> new file mode 100644
> index 00000000000..a3b1e2dd148
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/general/nmatch_1.c
> @@ -0,0 +1,30 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +
> +#include <arm_sve.h>
> +
> +svbool_t
> +test1 (svbool_t pg, svint16_t x, svint16_t y)
> +{
> +  return svand_z (svptrue_b8 (),
> +  svnmatch (pg, x, y),
> +  svptrue_b16 ());
> +}
> +
> +svbool_t
> +test2 (svbool_t pg, svint16_t x, svint16_t y)
> +{
> +  return svand_z (svptrue_b16 (),
> +  svnmatch (pg, x, y),
> +  svptrue_b8 ());
> +}
> +
> +svbool_t
> +test3 (svbool_t pg, svint16_t x, svint16_t y)
> +{
> +  return svand_z (svptrue_b16 (),
> +  svnmatch (pg, x, y),
> +  svptrue_b16 ());
> +}
> +
> +/* { dg-final { scan-assembler-not {\tand\t} } } */
> -- 
> 2.43.0
> 

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