There are many post-reload define_insn_and_split's that just append
a (clobber (reg:CC REG_CC)) to the pattern. Instead of repeating
the original patterns, avr_add_ccclobber (curr_insn) is used to do
that job.
This avoids repeating patterns all over the place, and splits that do
something different (like using a canonical form) stand out clearly.
Passes without new regressions.
Ok for trunk?
Johann
--
AVR: Add avr.cc::avr_add_ccclobber().
gcc/
* config/avr/avr.cc (avr_add_ccclobber): New function.
* config/avr/avr-protos.h (avr_add_ccclobber): New proto.
(DONE_ADD_CCC): New define.
--
AVR: Use avr_add_ccclobber / DONE_ADD_CCC in md instead of repeats.
There are many post-reload define_insn_and_split's that just append
a (clobber (reg:CC REG_CC)) to the pattern. Instead of repeating
the original patterns, avr_add_ccclobber (curr_insn) is used to do
that job.
This avoids repeating patterns all over the place, and splits that do
something different (like using a canonical form) stand out clearly.
gcc/
* gcc/config/avr.md (define_insn_and_split) [reload_completed]:
For splits that just append a (clobber (reg:CC REG_CC)) to
the pattern, use avr_add_ccclobber (curr_insn) instead of
repeating the original pattern.
* gcc/config/avr-dimode.md: Same.
* gcc/config/avr-fixed.md: Same. AVR: Add avr.cc::avr_add_ccclobber().
gcc/
* config/avr/avr.cc (avr_add_ccclobber): New function.
* config/avr/avr-protos.h (avr_add_ccclobber): New proto.
(DONE_ADD_CCC): New define.
diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h
index 37911e7d275..9aa00d39f1d 100644
--- a/gcc/config/avr/avr-protos.h
+++ b/gcc/config/avr/avr-protos.h
@@ -168,6 +168,8 @@ regmask (machine_mode mode, unsigned regno)
extern void avr_fix_inputs (rtx*, unsigned, unsigned);
extern bool avr_emit3_fix_outputs (rtx (*)(rtx,rtx,rtx), rtx*, unsigned, unsigned);
+extern rtx avr_add_ccclobber (rtx_insn *);
+#define DONE_ADD_CCC emit (avr_add_ccclobber (curr_insn)); DONE;
extern rtx lpm_reg_rtx;
extern rtx lpm_addr_reg_rtx;
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index 1fb59b624de..2afea952f08 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -411,6 +411,29 @@ avr_to_int_mode (rtx x)
}
+/* Return the pattern of INSN, but with added (clobber (reg:CC REG_CC)).
+ The pattern of INSN must be a PARALLEL or a SET. INSN is unchanged. */
+
+rtx
+avr_add_ccclobber (rtx_insn *insn)
+{
+ rtx pat = PATTERN (insn);
+ gcc_assert (GET_CODE (pat) == SET || GET_CODE (pat) == PARALLEL);
+
+ int newlen = GET_CODE (pat) == SET ? 2 : 1 + XVECLEN (pat, 0);
+ rtx newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (newlen));
+ rtx elt0 = GET_CODE (pat) == SET ? pat : XVECEXP (pat, 0, 0);
+
+ XVECEXP (newpat, 0, 0) = copy_rtx (elt0);
+ XVECEXP (newpat, 0, newlen - 1) = gen_rtx_CLOBBER (VOIDmode, cc_reg_rtx);
+
+ for (int i = 1; i < newlen - 1; ++i)
+ XVECEXP (newpat, 0, i) = copy_rtx (XVECEXP (pat, 0, i));
+
+ return newpat;
+}
+
+
/* Return true if hard register REG supports the ADIW and SBIW instructions. */
bool
AVR: Use avr_add_ccclobber / DONE_ADD_CCC in md instead of repeats.
There are many post-reload define_insn_and_split's that just append
a (clobber (reg:CC REG_CC)) to the pattern. Instead of repeating
the original patterns, avr_add_ccclobber (curr_insn) is used to do
that job.
This avoids repeating patterns all over the place, and splits that do
something different (like using a canonical form) stand out clearly.
gcc/
* gcc/config/avr.md (define_insn_and_split) [reload_completed]:
For splits that just append a (clobber (reg:CC REG_CC)) to
the pattern, use avr_add_ccclobber (curr_insn) instead of
repeating the original pattern.
* gcc/config/avr-dimode.md: Same.
* gcc/config/avr-fixed.md: Same.
diff --git a/gcc/config/avr/avr-dimode.md b/gcc/config/avr/avr-dimode.md
index 903bfbf42c8..67c5df43e54 100644
--- a/gcc/config/avr/avr-dimode.md
+++ b/gcc/config/avr/avr-dimode.md
@@ -101,10 +101,8 @@ (define_insn_and_split "add<mode>3_insn"
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8 ACC_A)
- (plus:ALL8 (reg:ALL8 ACC_A)
- (reg:ALL8 ACC_B)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*add<mode>3_insn"
[(set (reg:ALL8 ACC_A)
@@ -122,10 +120,8 @@ (define_insn_and_split "adddi3_const8_insn"
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:DI ACC_A)
- (plus:DI (reg:DI ACC_A)
- (sign_extend:DI (reg:QI REG_X))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*adddi3_const8_insn"
[(set (reg:DI ACC_A)
@@ -146,12 +142,10 @@ (define_insn_and_split "add<mode>3_const_insn"
(match_operand:ALL8 0 "const_operand" "n Ynn")))]
"avr_have_dimode
&& !s8_operand (operands[0], VOIDmode)"
- "#"
- "&& reload_completed"
- [(parallel [(set (reg:ALL8 ACC_A)
- (plus:ALL8 (reg:ALL8 ACC_A)
- (match_dup 0)))
- (clobber (reg:CC REG_CC))])])
+ "#"
+ "&& reload_completed"
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*add<mode>3_const_insn"
[(set (reg:ALL8 ACC_A)
@@ -211,10 +205,8 @@ (define_insn_and_split "sub<mode>3_insn"
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8 ACC_A)
- (minus:ALL8 (reg:ALL8 ACC_A)
- (reg:ALL8 ACC_B)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sub<mode>3_insn"
[(set (reg:ALL8 ACC_A)
@@ -236,10 +228,8 @@ (define_insn_and_split "sub<mode>3_const_insn"
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8 ACC_A)
- (minus:ALL8 (reg:ALL8 ACC_A)
- (match_dup 0)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sub<mode>3_const_insn"
[(set (reg:ALL8 ACC_A)
@@ -288,10 +278,8 @@ (define_insn_and_split "<code_stdname><mode>3_insn"
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8S ACC_A)
- (ss_addsub:ALL8S (reg:ALL8S ACC_A)
- (reg:ALL8S ACC_B)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3_insn"
[(set (reg:ALL8S ACC_A)
@@ -309,10 +297,8 @@ (define_insn_and_split "<code_stdname><mode>3_const_insn"
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8S ACC_A)
- (ss_addsub:ALL8S (reg:ALL8S ACC_A)
- (match_dup 0)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3_const_insn"
[(set (reg:ALL8S ACC_A)
@@ -361,10 +347,8 @@ (define_insn_and_split "<code_stdname><mode>3_insn"
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8U ACC_A)
- (us_addsub:ALL8U (reg:ALL8U ACC_A)
- (reg:ALL8U ACC_B)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3_insn"
[(set (reg:ALL8U ACC_A)
@@ -382,10 +366,8 @@ (define_insn_and_split "<code_stdname><mode>3_const_insn"
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8U ACC_A)
- (us_addsub:ALL8U (reg:ALL8U ACC_A)
- (match_operand:ALL8U 0 "const_operand" "n Ynn")))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3_const_insn"
[(set (reg:ALL8U ACC_A)
@@ -421,9 +403,8 @@ (define_insn_and_split "negdi2_insn"
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:DI ACC_A)
- (neg:DI (reg:DI ACC_A)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*negdi2_insn"
[(set (reg:DI ACC_A)
@@ -529,7 +510,7 @@ (define_insn_and_split "cbranch_const8_di2_split"
"avr_have_dimode"
"#"
"&& reload_completed"
- [(const_int 0)]
+ [(scratch)]
{
emit_insn (gen_compare_const8_di2 ());
emit_jump_insn (gen_conditional_jump (operands[0], operands[1]));
@@ -556,7 +537,7 @@ (define_insn_and_split "cbranch_const_<mode>2_split"
&& !s8_operand (operands[1], VOIDmode)"
"#"
"&& reload_completed"
- [(const_int 0)]
+ [(scratch)]
{
emit_insn (gen_compare_const_<mode>2 (operands[1], operands[3]));
emit_jump_insn (gen_conditional_jump (operands[0], operands[2]));
@@ -629,10 +610,8 @@ (define_insn_and_split "<code_stdname><mode>3_insn"
"avr_have_dimode"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL8 ACC_A)
- (di_shifts:ALL8 (reg:ALL8 ACC_A)
- (reg:QI 16)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3_insn"
[(set (reg:ALL8 ACC_A)
@@ -674,14 +653,10 @@ (define_insn_and_split "<extend_u>mulsidi3_insn"
(clobber (reg:HI REG_Z))]
"avr_have_dimode
&& AVR_HAVE_MUL"
- "#"
- "&& reload_completed"
- [(parallel [(set (reg:DI ACC_A)
- (mult:DI (any_extend:DI (reg:SI 18))
- (any_extend:DI (reg:SI 22))))
- (clobber (reg:HI REG_X))
- (clobber (reg:HI REG_Z))
- (clobber (reg:CC REG_CC))])])
+ "#"
+ "&& reload_completed"
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<extend_u>mulsidi3_insn"
[(set (reg:DI ACC_A)
diff --git a/gcc/config/avr/avr-fixed.md b/gcc/config/avr/avr-fixed.md
index ce46bebaf3d..22061fc5420 100644
--- a/gcc/config/avr/avr-fixed.md
+++ b/gcc/config/avr/avr-fixed.md
@@ -62,10 +62,8 @@ (define_insn_and_split "fract<FIXED_B:mode><FIXED_A:mode>2"
"<FIXED_B:MODE>mode != <FIXED_A:MODE>mode"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (fract_convert:FIXED_A
- (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fract<FIXED_B:mode><FIXED_A:mode>2"
[(set (match_operand:FIXED_A 0 "register_operand" "=r")
@@ -86,10 +84,8 @@ (define_insn_and_split "fractuns<FIXED_B:mode><FIXED_A:mode>2"
"<FIXED_B:MODE>mode != <FIXED_A:MODE>mode"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (unsigned_fract_convert:FIXED_A
- (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fractuns<FIXED_B:mode><FIXED_A:mode>2"
[(set (match_operand:FIXED_A 0 "register_operand" "=r")
@@ -124,10 +120,8 @@ (define_insn_and_split "<code_stdname><mode>3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ss_addsub:ALL124S (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3"
[(set (match_operand:ALL124S 0 "register_operand" "=??d,d")
@@ -149,10 +143,8 @@ (define_insn_and_split "<code_stdname><mode>3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (us_addsub:ALL124U (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3"
[(set (match_operand:ALL124U 0 "register_operand" "=??r,d")
@@ -189,9 +181,8 @@ (define_insn_and_split "ssnegqq2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ss_neg:QQ (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ssnegqq2"
[(set (match_operand:QQ 0 "register_operand" "=r")
@@ -207,9 +198,8 @@ (define_insn_and_split "ssabsqq2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ss_abs:QQ (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ssabsqq2"
[(set (match_operand:QQ 0 "register_operand" "=r")
@@ -241,9 +231,8 @@ (define_insn_and_split "*<code_stdname><mode>2_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL2S 24)
- (ss_abs_neg:ALL2S (reg:ALL2S 24)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>2"
[(set (reg:ALL2S 24)
@@ -261,9 +250,8 @@ (define_insn_and_split "*<code_stdname><mode>2_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL4S 22)
- (ss_abs_neg:ALL4S (reg:ALL4S 22)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>2"
[(set (reg:ALL4S 22)
@@ -296,10 +284,8 @@ (define_insn_and_split "mulqq3_enh"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:QQ (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulqq3_enh"
[(set (match_operand:QQ 0 "register_operand" "=r")
@@ -317,10 +303,8 @@ (define_insn_and_split "muluqq3_enh"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:UQQ (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*muluqq3_enh"
[(set (match_operand:UQQ 0 "register_operand" "=r")
@@ -377,12 +361,8 @@ (define_insn_and_split "*mulqq3.call_split"
"!AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:QQ 23)
- (mult:QQ (reg:QQ 24)
- (reg:QQ 25)))
- (clobber (reg:QI 22))
- (clobber (reg:HI 24))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulqq3.call"
[(set (reg:QQ 23)
@@ -425,11 +405,8 @@ (define_insn_and_split "*mul<mode>3.call_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL2QA 24)
- (mult:ALL2QA (reg:ALL2QA 18)
- (reg:ALL2QA 26)))
- (clobber (reg:HI 22))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mul<mode>3.call"
[(set (reg:ALL2QA 24)
@@ -468,10 +445,8 @@ (define_insn_and_split "*mul<mode>3.call_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL4A 24)
- (mult:ALL4A (reg:ALL4A 16)
- (reg:ALL4A 20)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mul<mode>3.call"
[(set (reg:ALL4A 24)
@@ -514,11 +489,8 @@ (define_insn_and_split "*<code><mode>3.call_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL1Q 24)
- (usdiv:ALL1Q (reg:ALL1Q 25)
- (reg:ALL1Q 22)))
- (clobber (reg:QI 25))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code><mode>3.call"
[(set (reg:ALL1Q 24)
@@ -560,12 +532,8 @@ (define_insn_and_split "*<code><mode>3.call_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL2QA 24)
- (usdiv:ALL2QA (reg:ALL2QA 26)
- (reg:ALL2QA 22)))
- (clobber (reg:HI 26))
- (clobber (reg:QI 21))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code><mode>3.call"
[(set (reg:ALL2QA 24)
@@ -608,12 +576,8 @@ (define_insn_and_split "*<code><mode>3.call_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL4A 22)
- (usdiv:ALL4A (reg:ALL4A 24)
- (reg:ALL4A 18)))
- (clobber (reg:HI 26))
- (clobber (reg:HI 30))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code><mode>3.call"
[(set (reg:ALL4A 22)
@@ -684,12 +648,8 @@ (define_insn_and_split "round<mode>3_const"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (unspec:ALL124QA [(match_dup 1)
- (match_dup 2)
- (const_int 0)]
- UNSPEC_ROUND))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*round<mode>3_const"
[(set (match_operand:ALL124QA 0 "register_operand" "=d")
@@ -714,11 +674,8 @@ (define_insn_and_split "*round<mode>3.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL1Q 24)
- (unspec:ALL1Q [(reg:ALL1Q 22)
- (reg:QI 24)] UNSPEC_ROUND))
- (clobber (reg:ALL1Q 22))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*round<mode>3.libgcc"
[(set (reg:ALL1Q 24)
@@ -740,11 +697,8 @@ (define_insn_and_split "*round<mode>3.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL2QA 24)
- (unspec:ALL2QA [(reg:ALL2QA 22)
- (reg:QI 24)] UNSPEC_ROUND))
- (clobber (reg:ALL2QA 22))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*round<mode>3.libgcc"
[(set (reg:ALL2QA 24)
@@ -766,11 +720,8 @@ (define_insn_and_split "*round<mode>3.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL4QA 22)
- (unspec:ALL4QA [(reg:ALL4QA 18)
- (reg:QI 24)] UNSPEC_ROUND))
- (clobber (reg:ALL4QA 18))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*round<mode>3.libgcc"
[(set (reg:ALL4QA 22)
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index f8bbdc76608..eb59816d421 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -574,9 +574,8 @@ (define_insn_and_split "load_<mode>_libgcc"
&& REG_Z == REGNO (XEXP (operands[0], 0))"
"#"
"&& reload_completed"
- [(parallel [(set (reg:MOVMODE 22)
- (match_dup 0))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*load_<mode>_libgcc"
[(set (reg:MOVMODE 22)
@@ -716,14 +715,8 @@ (define_insn_and_split "fxload_<mode>_libgcc"
|| avr_load_libgcc_insn_p (insn, ADDR_SPACE_FLASHX, true)"
"#"
"&& reload_completed"
- [(parallel [(set (reg:MOVMODE REG_22)
- (match_dup 0))
- (clobber (reg:QI REG_21))
- (clobber (reg:HI REG_Z))
- (clobber (reg:CC REG_CC))])]
- {
- operands[0] = SET_SRC (single_set (curr_insn));
- })
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fxload_<mode>_libgcc"
[(set (reg:MOVMODE REG_22)
@@ -853,9 +846,8 @@ (define_insn_and_split "mov<mode>_insn_split"
|| reg_or_0_operand (operands[1], <MODE>mode)"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (match_dup 1))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
;; "movqi_insn"
;; "movqq_insn" "movuqq_insn"
@@ -964,9 +956,8 @@ (define_insn_and_split "*mov<mode>_split"
|| reg_or_0_operand (operands[1], <MODE>mode)"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (match_dup 1))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mov<mode>"
[(set (match_operand:ALL2 0 "nonimmediate_operand" "=r,r ,r,m ,d,*r,q,r")
@@ -1137,9 +1128,8 @@ (define_insn_and_split "*movpsi_split"
|| const0_rtx == operands[1]"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (match_dup 1))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*movpsi"
[(set (match_operand:PSI 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")
@@ -1197,9 +1187,8 @@ (define_insn_and_split "*mov<mode>_split"
|| reg_or_0_operand (operands[1], <MODE>mode)"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (match_dup 1))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mov<mode>"
[(set (match_operand:ALL4 0 "nonimmediate_operand" "=r,r ,r ,Qm ,!d,r")
@@ -1245,9 +1234,8 @@ (define_insn_and_split "*movsf_split"
|| reg_or_0_operand (operands[1], SFmode)"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (match_dup 1))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*movsf"
[(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")
@@ -1326,16 +1314,8 @@ (define_insn_and_split "cpymem_<mode>"
""
"#"
"&& reload_completed"
- [(parallel [(set (mem:BLK (reg:HI REG_X))
- (mem:BLK (reg:HI REG_Z)))
- (unspec [(match_dup 0)]
- UNSPEC_CPYMEM)
- (use (match_dup 1))
- (clobber (reg:HI REG_X))
- (clobber (reg:HI REG_Z))
- (clobber (reg:QI LPM_REGNO))
- (clobber (match_dup 2))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*cpymem_<mode>"
[(set (mem:BLK (reg:HI REG_X))
@@ -1382,22 +1362,8 @@ (define_insn_and_split "cpymemx_<mode>"
""
"#"
"&& reload_completed"
- [(parallel [(set (mem:BLK (reg:HI REG_X))
- (match_dup 2))
- (unspec [(match_dup 0)]
- UNSPEC_CPYMEM)
- (use (reg:QIHI 24))
- (clobber (reg:HI REG_X))
- (clobber (reg:HI REG_Z))
- (clobber (reg:QI LPM_REGNO))
- (clobber (reg:HI 24))
- (clobber (reg:QI 23))
- (clobber (mem:QI (match_dup 1)))
- (clobber (reg:CC REG_CC))])]
- {
- rtx xset = XVECEXP (PATTERN (curr_insn), 0, 0);
- operands[2] = SET_SRC (xset);
- })
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*cpymemx_<mode>"
[(set (mem:BLK (reg:HI REG_X))
@@ -1461,13 +1427,8 @@ (define_insn_and_split "*clrmemqi_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (mem:BLK (match_dup 0))
- (const_int 0))
- (use (match_dup 1))
- (use (match_dup 2))
- (clobber (match_dup 3))
- (clobber (match_dup 4))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*clrmemqi"
[(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
@@ -1492,14 +1453,8 @@ (define_insn_and_split "*clrmemhi_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (mem:BLK (match_dup 0))
- (const_int 0))
- (use (match_dup 1))
- (use (match_dup 2))
- (clobber (match_dup 3))
- (clobber (match_dup 4))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "adiw,*")])
@@ -1550,13 +1505,8 @@ (define_insn_and_split "*strlenhi_split"
""
"#"
"&& reload_completed"
- [(parallel
- [(set (match_dup 0)
- (unspec:HI [(mem:BLK (match_dup 1))
- (const_int 0)
- (match_dup 2)]
- UNSPEC_STRLEN))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*strlenhi"
[(set (match_operand:HI 0 "register_operand" "=e")
@@ -1581,10 +1531,8 @@ (define_insn_and_split "add<mode>3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:ALL1 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*add<mode>3"
[(set (match_operand:ALL1 0 "register_operand" "=r,d ,r ,r ,r ,r")
@@ -1640,10 +1588,8 @@ (define_insn_and_split "*addhi3_zero_extend_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HI (zero_extend:HI (match_dup 1))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*addhi3_zero_extend"
[(set (match_operand:HI 0 "register_operand" "=r,*?r")
@@ -1663,10 +1609,8 @@ (define_insn_and_split "*addhi3_zero_extend1_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HI (match_dup 1)
- (zero_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*addhi3_zero_extend1"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -1684,10 +1628,8 @@ (define_insn_and_split "*addhi3_zero_extend.const_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HI (zero_extend:HI (match_dup 1))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*addhi3_zero_extend.const"
[(set (match_operand:HI 0 "register_operand" "=d")
@@ -1723,11 +1665,8 @@ (define_insn_and_split "*addhi3_zero_extend.ashift1.split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HI (ashift:HI (zero_extend:HI (match_dup 1))
- (const_int 1))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*addhi3_zero_extend.ashift1"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -1752,11 +1691,8 @@ (define_insn_and_split "*usum_widenqihi3_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HI (zero_extend:HI (match_dup 1))
- (zero_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
-
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*usum_widenqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -1774,10 +1710,8 @@ (define_insn_and_split "*udiff_widenqihi3_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:HI (zero_extend:HI (match_dup 1))
- (zero_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*udiff_widenqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -1909,11 +1843,8 @@ (define_insn_and_split "add<mode>3_clobber"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:ALL2 (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
;; "*addhi3_clobber"
;; "*addhq3_clobber" "*adduhq3_clobber"
@@ -1943,11 +1874,8 @@ (define_insn_and_split "add<mode>3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:ALL4 (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*add<mode>3"
[(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
@@ -1979,10 +1907,8 @@ (define_insn_and_split "*add<HISI:mode>3.<code>.<QIPSI:mode>_split"
&& (<HISI:SIZE> > 2 || <CODE> == SIGN_EXTEND)"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HISI (any_extend:HISI (match_dup 1))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
;; "*addhi3.sign_extend.qi"
;; "*addpsi3.zero_extend.qi" "*addpsi3.sign_extend.qi"
@@ -2019,10 +1945,8 @@ (define_insn_and_split "*sub<HISI:mode>3.<code>.<QIPSI:mode>_split"
"<HISI:SIZE> > <QIPSI:SIZE>"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:HISI (match_dup 1)
- (any_extend:HISI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
;; "*subhi3.zero_extend.qi" "*subhi3.sign_extend.qi"
;; "*subpsi3.zero_extend.qi" "*subpsi3.sign_extend.qi"
@@ -2053,11 +1977,8 @@ (define_insn_and_split "addpsi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3 ))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*addpsi3"
[(set (match_operand:PSI 0 "register_operand" "=??r,d ,d,r")
@@ -2079,10 +2000,8 @@ (define_insn_and_split "subpsi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*subpsi3"
[(set (match_operand:PSI 0 "register_operand" "=r")
@@ -2106,10 +2025,8 @@ (define_insn_and_split "sub<mode>3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:ALL1 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sub<mode>3"
[(set (match_operand:ALL1 0 "register_operand" "=??r,d ,r ,r ,r ,r")
@@ -2137,11 +2054,8 @@ (define_insn_and_split "sub<mode>3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:ALL2 (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sub<mode>3"
[(set (match_operand:ALL2 0 "register_operand" "=??r,d ,*r")
@@ -2167,11 +2081,8 @@ (define_insn_and_split "sub<mode>3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:ALL4 (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sub<mode>3"
[(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
@@ -2209,10 +2120,8 @@ (define_insn_and_split "*mulqi3_enh_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:QI (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulqi3_enh"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -2243,10 +2152,8 @@ (define_insn_and_split "*mulqi3_call_split"
"!AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:QI 24)
- (mult:QI (reg:QI 24) (reg:QI 22)))
- (clobber (reg:QI 22))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulqi3_call"
[(set (reg:QI 24)
@@ -2269,12 +2176,8 @@ (define_insn_and_split "<extend_su>mulqi3_highpart"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (truncate:QI
- (lshiftrt:HI (mult:HI (any_extend:HI (match_dup 1))
- (any_extend:HI (match_dup 2)))
- (const_int 8))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<extend_su>mulqi3_highpart"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -2405,12 +2308,9 @@ (define_insn_and_split "*add<QISI:mode>3.<code>0_split"
""
"#"
"&& reload_completed"
- [; *add<QISI:mode>3.<code>0
- (parallel [(set (match_dup 0)
- (plus:QISI (gelt:QISI (match_dup 1)
- (const_int 0))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ ; *add<QISI:mode>3.<code>0
+ [(scratch)]
+ { DONE_ADD_CCC })
;; *subqi3.lt0_split *subqi3.ge0_split
;; *subhi3.lt0_split *subhi3.ge0_split
@@ -2424,12 +2324,9 @@ (define_insn_and_split "*sub<QISI:mode>3.<code>0_split"
""
"#"
"&& reload_completed"
- [; *sub<QISI:mode>3.<code>0
- (parallel [(set (match_dup 0)
- (minus:QISI (match_dup 1)
- (gelt:QISI (match_dup 2)
- (const_int 0))))
- (clobber (reg:CC REG_CC))])])
+ ; *sub<QISI:mode>3.<code>0
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn_and_split "*umulqihi3.call_split"
@@ -2441,12 +2338,8 @@ (define_insn_and_split "*umulqihi3.call_split"
"!AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (mult:HI (zero_extend:HI (reg:QI 22))
- (zero_extend:HI (reg:QI 24))))
- (clobber (reg:QI 21))
- (clobber (reg:HI 22))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*umulqihi3.call"
[(set (reg:HI 24)
@@ -2469,10 +2362,8 @@ (define_insn_and_split "<extend_u>mulqihi3_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (any_extend:HI (match_dup 1))
- (any_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "<extend_u>mulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -2492,10 +2383,8 @@ (define_insn_and_split "usmulqihi3"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (zero_extend:HI (match_dup 1))
- (sign_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*usmulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -2517,10 +2406,8 @@ (define_insn_and_split "*sumulqihi3_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (sign_extend:HI (match_dup 1))
- (zero_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sumulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -2542,10 +2429,8 @@ (define_insn_and_split "*osmulqihi3_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (not:HI (zero_extend:HI (not:QI (match_dup 1))))
- (sign_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*osmulqihi3"
[(set (match_operand:HI 0 "register_operand" "=&r")
@@ -2566,10 +2451,8 @@ (define_insn_and_split "*oumulqihi3_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (not:HI (zero_extend:HI (not:QI (match_dup 1))))
- (zero_extend:HI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*oumulqihi3"
[(set (match_operand:HI 0 "register_operand" "=&r")
@@ -2596,11 +2479,8 @@ (define_insn_and_split "*maddqi4_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:QI (mult:QI (match_dup 1)
- (match_dup 2))
- (match_dup 3)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*maddqi4"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -2622,11 +2502,8 @@ (define_insn_and_split "*msubqi4_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:QI (match_dup 3)
- (mult:QI (match_dup 1)
- (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*msubqi4"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -2705,11 +2582,8 @@ (define_insn_and_split "*<extend_u>maddqihi4_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HI (mult:HI (any_extend:HI (match_dup 1))
- (any_extend:HI (match_dup 2)))
- (match_dup 3)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<extend_u>maddqihi4"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -2734,11 +2608,8 @@ (define_insn_and_split "*<extend_u>msubqihi4_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:HI (match_dup 3)
- (mult:HI (any_extend:HI (match_dup 1))
- (any_extend:HI (match_dup 2)))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<extend_u>msubqihi4"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -2765,11 +2636,8 @@ (define_insn_and_split "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4_
&& <any_extend:CODE> != <any_extend2:CODE>"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:HI (mult:HI (any_extend:HI (match_dup 1))
- (any_extend2:HI (match_dup 2)))
- (match_dup 3)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -2800,11 +2668,8 @@ (define_insn_and_split "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4_
&& <any_extend:CODE> != <any_extend2:CODE>"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (minus:HI (match_dup 3)
- (mult:HI (any_extend:HI (match_dup 1))
- (any_extend2:HI (match_dup 2)))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -3072,10 +2937,8 @@ (define_insn_and_split "*ashiftqihi2.signx.1_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashift:HI (sign_extend:HI (match_dup 1))
- (const_int 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ashiftqihi2.signx.1"
[(set (match_operand:HI 0 "register_operand" "=r,*r")
@@ -3153,10 +3016,8 @@ (define_insn_and_split "mulsqihi3"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (sign_extend:HI (match_dup 1))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulsqihi3"
[(set (match_operand:HI 0 "register_operand" "=&r")
@@ -3178,10 +3039,8 @@ (define_insn_and_split "muluqihi3"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (zero_extend:HI (match_dup 1))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*muluqihi3"
[(set (match_operand:HI 0 "register_operand" "=&r")
@@ -3205,10 +3064,8 @@ (define_insn_and_split "muloqihi3"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (not:HI (zero_extend:HI (not:QI (match_dup 1))))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*muloqihi3"
[(set (match_operand:HI 0 "register_operand" "=&r")
@@ -3277,10 +3134,8 @@ (define_insn_and_split "*mulhi3_enh_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:HI (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulhi3_enh"
[(set (match_operand:HI 0 "register_operand" "=&r")
@@ -3319,11 +3174,8 @@ (define_insn_and_split "*mulhi3_call_split"
"!AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (mult:HI (reg:HI 24) (reg:HI 22)))
- (clobber (reg:HI 22))
- (clobber (reg:QI 21))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulhi3_call"
[(set (reg:HI 24)
@@ -3719,11 +3571,8 @@ (define_insn_and_split "*mulsi3_call_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 22)
- (mult:SI (reg:SI 22)
- (reg:SI 18)))
- (clobber (reg:HI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn_and_split "*mulsi3_call_pr118012_split"
[(set (reg:SI 22)
@@ -3737,13 +3586,8 @@ (define_insn_and_split "*mulsi3_call_pr118012_split"
&& ! AVR_TINY"
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 22)
- (mult:SI (reg:SI 22)
- (reg:SI 18)))
- (clobber (reg:SI 18))
- (clobber (reg:HI 26))
- (clobber (reg:HI 30))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulsi3_call"
[(set (reg:SI 22)
@@ -3779,10 +3623,8 @@ (define_insn_and_split "*<extend_u>mulhisi3_call_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 22)
- (mult:SI (any_extend:SI (reg:HI 18))
- (any_extend:SI (reg:HI 26))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<extend_u>mulhisi3_call"
[(set (reg:SI 22)
@@ -3804,12 +3646,8 @@ (define_insn_and_split "*<extend_su>mulhi3_highpart_call_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (truncate:HI (lshiftrt:SI (mult:SI (any_extend:SI (reg:HI 18))
- (any_extend:SI (reg:HI 26)))
- (const_int 16))))
- (clobber (reg:HI 22))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<extend_su>mulhi3_highpart_call"
[(set (reg:HI 24)
@@ -3829,10 +3667,8 @@ (define_insn_and_split "*usmulhisi3_call_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 22)
- (mult:SI (zero_extend:SI (reg:HI 18))
- (sign_extend:SI (reg:HI 26))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*usmulhisi3_call"
[(set (reg:SI 22)
@@ -3850,10 +3686,8 @@ (define_insn_and_split "*mul<extend_su>hisi3_call_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 22)
- (mult:SI (any_extend:SI (reg:HI 26))
- (reg:SI 18)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mul<extend_su>hisi3_call"
[(set (reg:SI 22)
@@ -3871,10 +3705,8 @@ (define_insn_and_split "*mulohisi3_call_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 22)
- (mult:SI (not:SI (zero_extend:SI (not:HI (reg:HI 26))))
- (reg:SI 18)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulohisi3_call"
[(set (reg:SI 22)
@@ -3925,11 +3757,8 @@ (define_insn_and_split "*divmodqi4_call_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
- (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
- (clobber (reg:QI 22))
- (clobber (reg:QI 23))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*divmodqi4_call"
[(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
@@ -3969,10 +3798,8 @@ (define_insn_and_split "*udivmodqi4_call_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
- (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
- (clobber (reg:QI 23))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*udivmodqi4_call"
[(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
@@ -4013,11 +3840,8 @@ (define_insn_and_split "*divmodhi4_call_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
- (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
- (clobber (reg:HI 26))
- (clobber (reg:QI 21))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*divmodhi4_call"
[(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
@@ -4059,11 +3883,8 @@ (define_insn_and_split "*udivmodhi4_call_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
- (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
- (clobber (reg:HI 26))
- (clobber (reg:QI 21))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*udivmodhi4_call"
[(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
@@ -4112,10 +3933,8 @@ (define_insn_and_split "*umulqihipsi3_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:PSI (zero_extend:PSI (match_dup 1))
- (zero_extend:PSI (match_dup 2))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*umulqihipsi3"
[(set (match_operand:PSI 0 "register_operand" "=&r")
@@ -4139,10 +3958,8 @@ (define_insn_and_split "*umulhiqipsi3_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:PSI (zero_extend:PSI (match_dup 2))
- (zero_extend:PSI (match_dup 1))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*umulhiqipsi3"
[(set (match_operand:PSI 0 "register_operand" "=&r")
@@ -4229,10 +4046,8 @@ (define_insn_and_split "*mulsqipsi3.libgcc_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:PSI 18)
- (mult:PSI (sign_extend:PSI (reg:QI 25))
- (reg:PSI 22)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulsqipsi3.libgcc"
[(set (reg:PSI 18)
@@ -4253,13 +4068,8 @@ (define_insn_and_split "*mulpsi3.libgcc_split"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:PSI 22)
- (mult:PSI (reg:PSI 22)
- (reg:PSI 18)))
- (clobber (reg:QI 21))
- (clobber (reg:QI 25))
- (clobber (reg:HI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulpsi3.libgcc"
[(set (reg:PSI 22)
@@ -4311,12 +4121,8 @@ (define_insn_and_split "*divmodpsi4_call_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:PSI 22) (div:PSI (reg:PSI 22) (reg:PSI 18)))
- (set (reg:PSI 18) (mod:PSI (reg:PSI 22) (reg:PSI 18)))
- (clobber (reg:QI 21))
- (clobber (reg:QI 25))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*divmodpsi4_call"
[(set (reg:PSI 22) (div:PSI (reg:PSI 22) (reg:PSI 18)))
@@ -4360,12 +4166,8 @@ (define_insn_and_split "*udivmodpsi4_call_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:PSI 22) (udiv:PSI (reg:PSI 22) (reg:PSI 18)))
- (set (reg:PSI 18) (umod:PSI (reg:PSI 22) (reg:PSI 18)))
- (clobber (reg:QI 21))
- (clobber (reg:QI 25))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*udivmodpsi4_call"
[(set (reg:PSI 22) (udiv:PSI (reg:PSI 22) (reg:PSI 18)))
@@ -4411,11 +4213,8 @@ (define_insn_and_split "*divmodsi4_call_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
- (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
- (clobber (reg:HI 26))
- (clobber (reg:HI 30))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*divmodsi4_call"
[(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
@@ -4458,11 +4257,8 @@ (define_insn_and_split "*udivmodsi4_call_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
- (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
- (clobber (reg:HI 26))
- (clobber (reg:HI 30))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*udivmodsi4_call"
[(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
@@ -4484,10 +4280,8 @@ (define_insn_and_split "andqi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (and:QI (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*andqi3"
[(set (match_operand:QI 0 "register_operand" "=??r,d,*l ,r")
@@ -4511,11 +4305,8 @@ (define_insn_and_split "andhi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (and:HI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*andhi3"
[(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r ,r")
@@ -4545,11 +4336,8 @@ (define_insn_and_split "andpsi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (and:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*andpsi3"
[(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r ,r")
@@ -4580,11 +4368,8 @@ (define_insn_and_split "andsi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (and:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*andsi3"
[(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r ,r")
@@ -4634,10 +4419,8 @@ (define_insn_and_split "iorqi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ior:QI (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*iorqi3"
[(set (match_operand:QI 0 "register_operand" "=??r,d,*l")
@@ -4659,11 +4442,8 @@ (define_insn_and_split "iorhi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ior:HI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*iorhi3"
[(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r")
@@ -4691,11 +4471,8 @@ (define_insn_and_split "iorpsi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ior:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*iorpsi3"
[(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r")
@@ -4723,11 +4500,8 @@ (define_insn_and_split "iorsi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ior:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*iorsi3"
[(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r")
@@ -4758,10 +4532,8 @@ (define_insn_and_split "xorqi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (xor:QI (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*xorqi3"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -4780,11 +4552,8 @@ (define_insn_and_split "xorhi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (xor:HI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*xorhi3"
[(set (match_operand:HI 0 "register_operand" "=??r,r ,d ,r")
@@ -4810,11 +4579,8 @@ (define_insn_and_split "xorpsi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (xor:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*xorpsi3"
[(set (match_operand:PSI 0 "register_operand" "=??r,r ,d ,r")
@@ -4842,11 +4608,8 @@ (define_insn_and_split "xorsi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (xor:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*xorsi3"
[(set (match_operand:SI 0 "register_operand" "=??r,r ,d ,r")
@@ -5026,10 +4789,8 @@ (define_insn_and_split "*rotlqi3_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (rotate:QI (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*rotlqi3"
[(set (match_operand:QI 0 "register_operand" "=r,r,r ,r ,r ,r ,r ,r")
@@ -5099,10 +4860,8 @@ (define_insn_and_split "*rotlhi2.1_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (rotate:HI (match_dup 1)
- (const_int 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*rotlhi2.1"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -5120,10 +4879,8 @@ (define_insn_and_split "*rotlhi2.15_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (rotate:HI (match_dup 1)
- (const_int 15)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*rotlhi2.15"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -5141,10 +4898,8 @@ (define_insn_and_split "*rotlpsi2.1_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (rotate:PSI (match_dup 1)
- (const_int 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*rotlpsi2.1"
[(set (match_operand:PSI 0 "register_operand" "=r")
@@ -5162,10 +4917,8 @@ (define_insn_and_split "*rotlpsi2.23_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (rotate:PSI (match_dup 1)
- (const_int 23)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*rotlpsi2.23"
[(set (match_operand:PSI 0 "register_operand" "=r")
@@ -5183,10 +4936,8 @@ (define_insn_and_split "*rotlsi2.1_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (rotate:SI (match_dup 1)
- (const_int 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*rotlsi2.1"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -5204,10 +4955,8 @@ (define_insn_and_split "*rotlsi2.31_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (rotate:SI (match_dup 1)
- (const_int 31)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*rotlsi2.31"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -5239,7 +4988,7 @@ (define_insn_and_split "*rotw<mode>"
&& 0 == INTVAL (operands[2]) % 16"
"#"
"&& reload_completed"
- [(const_int 0)]
+ [(scratch)]
{
avr_rotate_bytes (operands);
DONE;
@@ -5263,7 +5012,7 @@ (define_insn_and_split "*rotb<mode>"
&& 0 == INTVAL (operands[2]) % 16))"
"#"
"&& reload_completed"
- [(const_int 0)]
+ [(scratch)]
{
avr_rotate_bytes (operands);
DONE;
@@ -5363,10 +5112,8 @@ (define_insn_and_split "*ashl<mode>3_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashift:ALL1 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ashl<mode>3"
[(set (match_operand:ALL1 0 "register_operand" "=r,r ,r ,r,r")
@@ -5390,11 +5137,8 @@ (define_insn_and_split "ashl<mode>3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashift:ALL2 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*,*")])
;; "*ashlhi3"
@@ -5506,11 +5250,8 @@ (define_insn_and_split "ashl<mode>3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashift:ALL4 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*,*")])
(define_insn "*ashl<mode>3"
@@ -5749,12 +5490,8 @@ (define_insn_and_split "*ashlpsi3_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashift:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*")])
(define_insn "*ashlpsi3"
@@ -5808,10 +5545,8 @@ (define_insn_and_split "ashr<mode>3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashiftrt:ALL1 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ashr<mode>3"
[(set (match_operand:ALL1 0 "register_operand" "=r,r ,r ,r")
@@ -5835,11 +5570,8 @@ (define_insn_and_split "ashr<mode>3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashiftrt:ALL2 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*,*")])
;; "*ashrhi3"
@@ -5866,12 +5598,8 @@ (define_insn_and_split "ashrpsi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashiftrt:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*")])
(define_insn "*ashrpsi3"
@@ -5898,11 +5626,8 @@ (define_insn_and_split "ashr<mode>3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ashiftrt:ALL4 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*,*")])
(define_insn "*ashr<mode>3"
@@ -6013,10 +5738,8 @@ (define_insn_and_split "*lshr<mode>3_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (lshiftrt:ALL1 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*lshr<mode>3"
[(set (match_operand:ALL1 0 "register_operand" "=r,r ,r ,r,r")
@@ -6039,11 +5762,8 @@ (define_insn_and_split "lshr<mode>3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (lshiftrt:ALL2 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*,*")])
(define_insn "*lshr<mode>3"
@@ -6066,12 +5786,8 @@ (define_insn_and_split "lshrpsi3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (lshiftrt:PSI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 3))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*")])
(define_insn "*lshrpsi3"
@@ -6098,11 +5814,8 @@ (define_insn_and_split "lshr<mode>3"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (lshiftrt:ALL4 (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,*,3op,*,*")])
(define_insn "*lshr<mode>3"
@@ -6217,9 +5930,8 @@ (define_insn_and_split "absqi2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (abs:QI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*absqi2"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -6237,9 +5949,8 @@ (define_insn_and_split "abssf2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (abs:SF (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*abssf2"
[(set (match_operand:SF 0 "register_operand" "=d,r")
@@ -6260,9 +5971,8 @@ (define_insn_and_split "negqi2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (neg:QI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*negqi2"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -6278,9 +5988,8 @@ (define_insn_and_split "*negqihi2_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (neg:HI (sign_extend:HI (match_dup 1))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*negqihi2"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -6296,9 +6005,8 @@ (define_insn_and_split "neghi2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (neg:HI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*neghi2"
[(set (match_operand:HI 0 "register_operand" "=r,&r")
@@ -6316,9 +6024,8 @@ (define_insn_and_split "negpsi2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (neg:PSI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*negpsi2"
[(set (match_operand:PSI 0 "register_operand" "=!d,r,&r")
@@ -6337,10 +6044,8 @@ (define_insn_and_split "negsi2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (neg:SI (match_dup 1)))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "*,*,mov,movw")])
(define_insn "*negsi2.libgcc"
@@ -6371,9 +6076,8 @@ (define_insn_and_split "negsf2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (neg:SF (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*negsf2"
[(set (match_operand:SF 0 "register_operand" "=d,r")
@@ -6394,9 +6098,8 @@ (define_insn_and_split "one_cmplqi2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (not:QI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*one_cmplqi2"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -6412,9 +6115,8 @@ (define_insn_and_split "one_cmplhi2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (not:HI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*one_cmplhi2"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -6431,9 +6133,8 @@ (define_insn_and_split "one_cmplpsi2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (not:PSI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*one_cmplpsi2"
[(set (match_operand:PSI 0 "register_operand" "=r")
@@ -6449,9 +6150,8 @@ (define_insn_and_split "one_cmplsi2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (not:SI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -6480,9 +6180,8 @@ (define_insn_and_split "extendqihi2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (sign_extend:HI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*extendqihi2"
[(set (match_operand:HI 0 "register_operand" "=r,r")
@@ -6501,9 +6200,8 @@ (define_insn_and_split "extendqipsi2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (sign_extend:PSI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*extendqipsi2"
[(set (match_operand:PSI 0 "register_operand" "=r,r")
@@ -6522,9 +6220,8 @@ (define_insn_and_split "extendqisi2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (sign_extend:SI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -6543,9 +6240,8 @@ (define_insn_and_split "extendhipsi2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (sign_extend:PSI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*extendhipsi2"
[(set (match_operand:PSI 0 "register_operand" "=r,r")
@@ -6564,9 +6260,8 @@ (define_insn_and_split "extendhisi2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (sign_extend:SI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -6585,9 +6280,8 @@ (define_insn_and_split "extendpsisi2"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (sign_extend:SI (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*extendpsisi2"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -7668,17 +7362,8 @@ (define_insn_and_split "sbrx_branch<mode>_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (if_then_else
- (match_op_dup 0
- [(zero_extract:QIDI
- (match_dup 1)
- (const_int 1)
- (match_dup 2))
- (const_int 0)])
- (label_ref (match_dup 3))
- (pc)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sbrx_branch<mode>"
[(set (pc)
@@ -7721,13 +7406,8 @@ (define_insn_and_split "*sbrx_and_branch<mode>_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (if_then_else (match_op_dup 0 [(and:QISI (match_dup 1)
- (match_dup 2))
- (const_int 0)])
- (label_ref (match_dup 3))
- (pc)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sbrx_and_branch<mode>"
[(set (pc)
@@ -7968,14 +7648,8 @@ (define_insn_and_split "*tablejump_split"
"!AVR_HAVE_EIJMP_EICALL"
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (unspec:HI [(match_dup 0)]
- UNSPEC_INDEX_JMP))
- (use (label_ref (match_dup 1)))
- (clobber (match_dup 2))
- (clobber (const_int 0))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "rjmp,rjmp,jmp")])
(define_insn "*tablejump"
@@ -8004,14 +7678,8 @@ (define_insn_and_split "*tablejump.3byte-pc_split"
"AVR_HAVE_EIJMP_EICALL"
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (unspec:HI [(reg:HI REG_Z)]
- UNSPEC_INDEX_JMP))
- (use (label_ref (match_dup 0)))
- (clobber (reg:HI REG_Z))
- (clobber (reg:QI 24))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "eijmp")])
@@ -8182,17 +7850,8 @@ (define_insn_and_split "*sbix_branch_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (if_then_else
- (match_operator 0 "eqne_operator"
- [(zero_extract:QIHI
- (mem:QI (match_dup 1))
- (const_int 1)
- (match_dup 2))
- (const_int 0)])
- (label_ref (match_dup 3))
- (pc)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sbix_branch"
[(set (pc)
@@ -8230,14 +7889,8 @@ (define_insn_and_split "*sbix_branch_bit7_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (if_then_else
- (match_operator 0 "gelt_operator"
- [(mem:QI (match_dup 1))
- (const_int 0)])
- (label_ref (match_dup 2))
- (pc)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sbix_branch_bit7"
[(set (pc)
@@ -8277,17 +7930,8 @@ (define_insn_and_split "*sbix_branch_tmp_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (if_then_else
- (match_operator 0 "eqne_operator"
- [(zero_extract:QIHI
- (mem:QI (match_dup 1))
- (const_int 1)
- (match_dup 2))
- (const_int 0)])
- (label_ref (match_dup 3))
- (pc)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sbix_branch_tmp"
[(set (pc)
@@ -8324,14 +7968,8 @@ (define_insn_and_split "*sbix_branch_tmp_bit7_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (pc)
- (if_then_else
- (match_operator 0 "gelt_operator"
- [(mem:QI (match_dup 1))
- (const_int 0)])
- (label_ref (match_dup 2))
- (pc)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sbix_branch_tmp_bit7"
[(set (pc)
@@ -8784,13 +8422,8 @@ (define_insn_and_split "delay_cycles_1"
""
"#"
"&& reload_completed"
- [(parallel [(unspec_volatile [(match_dup 0)
- (const_int 1)]
- UNSPECV_DELAY_CYCLES)
- (set (match_dup 1)
- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
- (clobber (match_dup 2))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*delay_cycles_1"
[(unspec_volatile [(match_operand:QI 0 "const_int_operand" "n")
@@ -8816,14 +8449,8 @@ (define_insn_and_split "delay_cycles_2"
""
"#"
"&& reload_completed"
- [(parallel [(unspec_volatile [(match_dup 0)
- (const_int 2)]
- UNSPECV_DELAY_CYCLES)
- (set (match_dup 1)
- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
- (clobber (match_dup 2))
- (clobber (reg:CC REG_CC))])]
- ""
+ [(scratch)]
+ { DONE_ADD_CCC }
[(set_attr "isa" "adiw,no_adiw")])
(define_insn "*delay_cycles_2"
@@ -8853,15 +8480,8 @@ (define_insn_and_split "delay_cycles_3"
""
"#"
"&& reload_completed"
- [(parallel [(unspec_volatile [(match_dup 0)
- (const_int 3)]
- UNSPECV_DELAY_CYCLES)
- (set (match_dup 1)
- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
- (clobber (match_dup 2))
- (clobber (match_dup 3))
- (clobber (match_dup 4))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*delay_cycles_3"
[(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
@@ -8896,16 +8516,8 @@ (define_insn_and_split "delay_cycles_4"
""
"#"
"&& reload_completed"
- [(parallel [(unspec_volatile [(match_dup 0)
- (const_int 4)]
- UNSPECV_DELAY_CYCLES)
- (set (match_dup 1)
- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
- (clobber (match_dup 2))
- (clobber (match_dup 3))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*delay_cycles_4"
[(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
@@ -8942,12 +8554,8 @@ (define_insn_and_split "insert_bits"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (unspec:QI [(match_dup 1)
- (match_dup 2)
- (match_dup 3)]
- UNSPEC_INSERT_BITS))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*insert_bits"
[(set (match_operand:QI 0 "register_operand" "=r ,d ,r")
@@ -9235,9 +8843,8 @@ (define_insn_and_split "*parityhi2.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (parity:HI (reg:HI 24)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*parityhi2.libgcc"
[(set (reg:HI 24)
@@ -9253,9 +8860,8 @@ (define_insn_and_split "*parityqihi2.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (zero_extend:HI (parity:QI (reg:QI 24))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*parityqihi2.libgcc"
[(set (reg:HI 24)
@@ -9271,9 +8877,8 @@ (define_insn_and_split "*paritysihi2.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (truncate:HI (parity:SI (reg:SI 22))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*paritysihi2.libgcc"
[(set (reg:HI 24)
@@ -9329,9 +8934,8 @@ (define_insn_and_split "*popcounthi2.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (popcount:HI (reg:HI 24)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*popcounthi2.libgcc"
[(set (reg:HI 24)
@@ -9347,9 +8951,8 @@ (define_insn_and_split "*popcountsi2.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (truncate:HI (popcount:SI (reg:SI 22))))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*popcountsi2.libgcc"
[(set (reg:HI 24)
@@ -9365,9 +8968,8 @@ (define_insn_and_split "*popcountqi2.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:QI 24)
- (popcount:QI (reg:QI 24)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*popcountqi2.libgcc"
[(set (reg:QI 24)
@@ -9421,10 +9023,8 @@ (define_insn_and_split "*clzhi2.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (clz:HI (reg:HI 24)))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*clzhi2.libgcc"
[(set (reg:HI 24)
@@ -9442,10 +9042,8 @@ (define_insn_and_split "*clzsihi2.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (truncate:HI (clz:SI (reg:SI 22))))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*clzsihi2.libgcc"
[(set (reg:HI 24)
@@ -9490,10 +9088,8 @@ (define_insn_and_split "*ctzhi2.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (ctz:HI (reg:HI 24)))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ctzhi2.libgcc"
[(set (reg:HI 24)
@@ -9512,11 +9108,8 @@ (define_insn_and_split "*ctzsihi2.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (truncate:HI (ctz:SI (reg:SI 22))))
- (clobber (reg:QI 22))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ctzsihi2.libgcc"
[(set (reg:HI 24)
@@ -9562,10 +9155,8 @@ (define_insn_and_split "*ffshi2.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (ffs:HI (reg:HI 24)))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ffshi2.libgcc"
[(set (reg:HI 24)
@@ -9584,11 +9175,8 @@ (define_insn_and_split "*ffssihi2.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 24)
- (truncate:HI (ffs:SI (reg:SI 22))))
- (clobber (reg:QI 22))
- (clobber (reg:QI 26))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ffssihi2.libgcc"
[(set (reg:HI 24)
@@ -9633,9 +9221,8 @@ (define_insn_and_split "*bswapsi2.libgcc_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:SI 22)
- (bswap:SI (reg:SI 22)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*bswapsi2.libgcc"
[(set (reg:SI 22)
@@ -9742,11 +9329,8 @@ (define_insn_and_split "fmul_insn"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (unspec:HI [(match_dup 1)
- (match_dup 2)]
- UNSPEC_FMUL))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fmul_insn"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -9768,11 +9352,8 @@ (define_insn_and_split "*fmul.call_split"
"!AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 22)
- (unspec:HI [(reg:QI 24)
- (reg:QI 25)] UNSPEC_FMUL))
- (clobber (reg:HI 24))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fmul.call"
[(set (reg:HI 22)
@@ -9814,11 +9395,8 @@ (define_insn_and_split "fmuls_insn"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (unspec:HI [(match_dup 1)
- (match_dup 2)]
- UNSPEC_FMULS))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fmuls_insn"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -9840,11 +9418,8 @@ (define_insn_and_split "*fmuls.call_split"
"!AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 22)
- (unspec:HI [(reg:QI 24)
- (reg:QI 25)] UNSPEC_FMULS))
- (clobber (reg:HI 24))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fmuls.call"
[(set (reg:HI 22)
@@ -9886,11 +9461,8 @@ (define_insn_and_split "fmulsu_insn"
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (unspec:HI [(match_dup 1)
- (match_dup 2)]
- UNSPEC_FMULSU))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fmulsu_insn"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -9912,11 +9484,8 @@ (define_insn_and_split "*fmulsu.call_split"
"!AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:HI 22)
- (unspec:HI [(reg:QI 24)
- (reg:QI 25)] UNSPEC_FMULSU))
- (clobber (reg:HI 24))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fmulsu.call"
[(set (reg:HI 22)
@@ -10037,11 +9606,8 @@ (define_insn_and_split "*insv.reg_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (zero_extract:QI (match_dup 0)
- (const_int 1)
- (match_dup 1))
- (match_dup 2))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*insv.reg"
[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r,d,d,l,l")
@@ -10478,11 +10044,8 @@ (define_insn_and_split "*extzv.not_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (zero_extract:QI (not:QI (match_dup 1))
- (const_int 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*extzv.not"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -10619,11 +10182,8 @@ (define_insn_and_split "*insv.any_shift.<mode>_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (and:QISI (any_shift:QISI (match_dup 1)
- (match_dup 2))
- (match_dup 3)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*insv.any_shift.<mode>"
[(set (match_operand:QISI 0 "register_operand" "=r")
@@ -10686,11 +10246,8 @@ (define_insn_and_split "*sextr.<QISI:mode>.<QISI2:mode>_split"
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (sign_extract:QISI (match_dup 1)
- (const_int 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*sextr.<QISI:mode>.<QISI2:mode>"
[(set (match_operand:QISI 0 "register_operand" "=r")
