Thanks Jeff. > OK. Any change we could get run test for this in addition to the scanners?
I tried to add run test target this but seems happen to work here for mulhsu. Here we only cares the result(high bits of mul) has values or not, looks like mulhsu will not result in correctness problem. Take uint8_t as example, mulhu (127, 2) = 0x0, it has no value in high 8 bits. mulhsu (127, 2) = 0x0, it has no value in high 8 bits. mulhu (128, 2) = 0x1, it has value in high 8 bits. mulhsu (-128, 2) = 0xff, it has value in high 8 bits. mulhu (129, 2) = 0x1, it has value in high 8 bits. mulhsu (-127, 2) = 0xff, it has value in high 8 bits. Pan -----Original Message----- From: Jeff Law <jeffreya...@gmail.com> Sent: Monday, August 4, 2025 9:33 AM To: Li, Pan2 <pan2...@intel.com>; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp....@gmail.com; Chen, Ken <ken.c...@intel.com>; Liu, Hongtao <hongtao....@intel.com> Subject: Re: [PATCH v1] RISC-V: Fix scalar code-gen of unsigned SAT_MUL On 7/30/25 11:22 PM, pan2...@intel.com wrote: > From: Pan Li <pan2...@intel.com> > > The previous code-gen of scalar unsigned SAT_MUL, aka usmul. > Leverage the mulhs by mistake, it should be mulhu for the > hight bit result of mul. Thus, this patch would like to make > it correct. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_expand_xmode_usmul): Take > umulhu for high bits mul result. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c: Add mulhu > asm check. > * gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c: Ditto. OK. Any change we could get run test for this in addition to the scanners? jeff
