From: Pan Li <pan2...@intel.com>
This patch would like to combine the vec_duplicate + vaadd.vv to the
vaadd.vx. From example as below code. The related pattern will depend
on the cost of vec_duplicate from GR2VR. Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.
Assume we have example code like below, GR2VR cost is 0.
#define DEF_VX_MERGE_0(T) \
void \
test_vx_merge_##T##_case_0 (T * restrict out, T * restrict in, \
T x, unsigned n) \
{ \
for (unsigned i = 0; i < n; i++) \
{ \
if (i % 2 == 0) \
out[i] = x; \
else \
out[i] = in[i]; \
} \
}
DEF_VX_MERGE_0(int32_t)
Before this patch:
11 │ beq a3,zero,.L8
12 │ vsetvli a5,zero,e32,m1,ta,ma
13 │ vmv.v.x v2,a2
...
16 │ .L3:
17 │ vsetvli a5,a3,e32,m1,ta,ma
...
22 │ vmerge.vvm v1,v1,v2,v0
...
25 │ bne a3,zero,.L3
After this patch:
11 │ beq a3,zero,.L8
...
14 │ .L3:
15 │ vsetvli a5,a3,e32,m1,ta,ma
...
20 │ vmerge.vxm v1,v1,a2,v0
...
23 │ bne a3,zero,.L3
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*merge_vx_<mode>): Add new
pattern to combine the vmerge.vxm.
* config/riscv/riscv.cc (get_vector_binary_rtx_cost): Add
REG or VEC_DUPLICATE handing.
(riscv_rtx_costs): Add vmerge handing for vec_dup.
Signed-off-by: Pan Li <pan2...@intel.com>
---
gcc/config/riscv/autovec-opt.md | 18 +++++++++++++++
gcc/config/riscv/riscv.cc | 39 +++++++++++++++++++++++++--------
2 files changed, 48 insertions(+), 9 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 65319960bc0..4559d25ff73 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1782,6 +1782,24 @@ (define_insn_and_split "*<sat_op_vdup_v>_vx_<mode>"
}
[(set_attr "type" "vaalu")])
+(define_insn_and_split "*merge_vx_<mode>"
+ [(set (match_operand:V_VLSI 0 "register_operand")
+ (if_then_else:V_VLSI
+ (match_operand:<VM> 3 "vector_mask_operand")
+ (vec_duplicate:V_VLSI
+ (match_operand:<VEL> 2 "reg_or_int_operand"))
+ (match_operand:V_VLSI 1 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ insn_code icode = code_for_pred_merge_scalar (<MODE>mode);
+ riscv_vector::emit_vlmax_insn (icode, riscv_vector::MERGE_OP, operands);
+ DONE;
+ }
+ [(set_attr "type" "vimerge")])
+
;;
=============================================================================
;; Combine vec_duplicate + op.vv to op.vf
;; Include
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0a9fcef3702..a614499e0fd 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3971,15 +3971,20 @@ get_vector_binary_rtx_cost (rtx x, int scalar2vr_cost)
rtx op_0;
rtx op_1;
- if (GET_CODE (x) == UNSPEC)
- {
- op_0 = XVECEXP (x, 0, 0);
- op_1 = XVECEXP (x, 0, 1);
- }
- else
+ switch (GET_CODE (x))
{
- op_0 = XEXP (x, 0);
- op_1 = XEXP (x, 1);
+ case REG:
+ return COSTS_N_INSNS (1);
+ case VEC_DUPLICATE:
+ return (scalar2vr_cost + 1) * COSTS_N_INSNS (1);
+ case UNSPEC:
+ op_0 = XVECEXP (x, 0, 0);
+ op_1 = XVECEXP (x, 0, 1);
+ break;
+ default:
+ op_0 = XEXP (x, 0);
+ op_1 = XEXP (x, 1);
+ break;
}
if (GET_CODE (op_0) == VEC_DUPLICATE
@@ -4021,7 +4026,23 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
outer_code, int opno ATTRIBUTE_UN
break;
case IF_THEN_ELSE:
{
- rtx op = XEXP (x, 1);
+ rtx op_0 = XEXP (x, 0);
+ rtx op_1 = XEXP (x, 1);
+ rtx op_2 = XEXP (x, 2);
+ rtx_code code_1 = GET_CODE (op_1);
+ rtx_code code_2 = GET_CODE (op_2);
+
+ if (REG_P (op_0)
+ && GET_MODE_CLASS (GET_MODE (op_0)) == MODE_VECTOR_BOOL
+ && ((code_1 == VEC_DUPLICATE && REG_P (op_2))
+ || (code_2 == VEC_DUPLICATE && REG_P (op_1))))
+ {
+ rtx op = GET_CODE (op_1) == VEC_DUPLICATE ? op_1 : op_2;
+ *total = get_vector_binary_rtx_cost (op, scalar2vr_cost);
+ break;
+ }
+
+ rtx op = op_1;
switch (GET_CODE (op))
{
--
2.43.0
