From: Pan Li <pan2...@intel.com>
This patch would like to try to match the the unsigned
SAT_MUL form 3, aka below:
#define DEF_SAT_U_MUL_FMT_3(NT, WT) \
NT __attribute__((noinline)) \
sat_u_mul_##NT##_from_##WT##_fmt_3 (NT a, NT b) \
{ \
WT x = (WT)a * (WT)b; \
if ((x >> sizeof(a) * 8) == 0) \
return (NT)x; \
else \
return (NT)-1; \
}
The NT is uint8_t, uint16_t, uint32_t and uint64_t, while the WT
is uint16_t, uint32_t, uint64_t and uint128_t.
Before this series if backend implemented usmul, we have:
14 │ <bb 2> [local count: 1073741824]:
15 │ _1 = (long unsigned int) a_5(D);
16 │ _2 = (long unsigned int) b_6(D);
17 │ x_7 = _1 * _2;
18 │ _3 = x_7 >> 32;
19 │ if (_3 == 0)
20 │ goto <bb 3>; [50.00%]
21 │ else
22 │ goto <bb 4>; [50.00%]
23 │
24 │ <bb 3> [local count: 536870912]:
25 │
26 │ <bb 4> [local count: 1073741824]:
27 │ # _8 = PHI <x_7(3), 4294967295(2)>
28 │ prephitmp_11 = (unsigned int) _8;
29 │ return prephitmp_11;
After this series if backend implemented usmul, we have:
26 │ <bb 4> [local count: 1073741824]:
27 │ # _8 = PHI <x_7(3), 4294967295(2)>
28 │ prephitmp_11 = .SAT_MUL (a_5(D), b_6(D));
The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.
2. The x86 bootstrap tests.
3. The x86 fully regression tests.
Pan Li (2):
Match: Add form 3 for unsigned SAT_MUL
RISC-V: Add testcase for scalar unsigned SAT_MUL form 3
gcc/match.pd | 27 ++++++++++++++++++-
.../gcc.target/riscv/sat/sat_arith.h | 16 +++++++++++
.../riscv/sat/sat_u_mul-4-u16-from-u128.c | 12 +++++++++
.../riscv/sat/sat_u_mul-4-u16-from-u32.c | 12 +++++++++
.../riscv/sat/sat_u_mul-4-u16-from-u64.c | 12 +++++++++
.../riscv/sat/sat_u_mul-4-u16-from-u64.rv32.c | 12 +++++++++
.../riscv/sat/sat_u_mul-4-u32-from-u128.c | 12 +++++++++
.../riscv/sat/sat_u_mul-4-u32-from-u64.c | 12 +++++++++
.../riscv/sat/sat_u_mul-4-u32-from-u64.rv32.c | 13 +++++++++
.../riscv/sat/sat_u_mul-4-u64-from-u128.c | 13 +++++++++
.../riscv/sat/sat_u_mul-4-u8-from-u128.c | 12 +++++++++
.../riscv/sat/sat_u_mul-4-u8-from-u16.c | 12 +++++++++
.../riscv/sat/sat_u_mul-4-u8-from-u32.c | 12 +++++++++
.../riscv/sat/sat_u_mul-4-u8-from-u64.c | 12 +++++++++
.../riscv/sat/sat_u_mul-4-u8-from-u64.rv32.c | 12 +++++++++
.../riscv/sat/sat_u_mul-run-4-u16-from-u128.c | 16 +++++++++++
.../riscv/sat/sat_u_mul-run-4-u16-from-u32.c | 16 +++++++++++
.../riscv/sat/sat_u_mul-run-4-u16-from-u64.c | 16 +++++++++++
.../sat/sat_u_mul-run-4-u16-from-u64.rv32.c | 16 +++++++++++
.../riscv/sat/sat_u_mul-run-4-u32-from-u128.c | 16 +++++++++++
.../riscv/sat/sat_u_mul-run-4-u32-from-u64.c | 16 +++++++++++
.../sat/sat_u_mul-run-4-u32-from-u64.rv32.c | 16 +++++++++++
.../riscv/sat/sat_u_mul-run-4-u64-from-u128.c | 16 +++++++++++
.../riscv/sat/sat_u_mul-run-4-u8-from-u128.c | 16 +++++++++++
.../riscv/sat/sat_u_mul-run-4-u8-from-u16.c | 16 +++++++++++
.../riscv/sat/sat_u_mul-run-4-u8-from-u32.c | 16 +++++++++++
.../riscv/sat/sat_u_mul-run-4-u8-from-u64.c | 16 +++++++++++
.../sat/sat_u_mul-run-4-u8-from-u64.rv32.c | 16 +++++++++++
28 files changed, 408 insertions(+), 1 deletion(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.rv32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.rv32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u64-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u128.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.rv32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.rv32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.rv32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u64-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.rv32.c
--
2.43.0
