This patch add support for XAndesvbfhcvt ISA extension.
This extension defines instructions to perform vector floating-point
conversion between the BFLOAT16 floating-point data and the IEEE-754 32-bit
single-precision floating-point (SP) data in a vector register.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
Turn on VECTOR_ELEN_BF_16 for XAndesvbfhcvt.
* config.gcc: Add extra_objs andes-vector-builtins-bases.o
and extra_headers andes_vector.h.
* config/riscv/generic-vector-ooo.md:
Add nds_vfwcvtbf16 and nds_vfncvtbf16.
* config/riscv/riscv-vector-builtins-shapes.cc
(BASE_NAME_MAX_LEN): Increase size to 20.
* config/riscv/riscv-vector-builtins.cc
(f32_to_bf16_nf_w_ops): New operand information.
(f32_to_bf16_nf_w_ops): New operand information.
(DEF_RVV_FUNCTION): New def.
* config/riscv/riscv-vector-builtins.def (bf16): Ditto.
* config/riscv/riscv-vector-builtins.h (enum required_ext): Ditto.
(required_ext_to_isa_name): Add case XANDESVBFHCVT_EXT.
(required_extensions_specified): Ditto.
* config/riscv/riscv.md: New attr nds_vfwcvtbf16 and nds_vfncvtbf16.
* config/riscv/t-riscv: Add andes-vector-builtins-functions.def,
andes-vector-builtins-bases.h and andes-vector-builtins-bases.o.
* config/riscv/vector-iterators.md (NDS_VWEXTBF): New iterator.
(NDS_V_DOUBLE_TRUNC_BF): New attr.
* config/riscv/andes-vector-builtins-bases.cc: New file.
* config/riscv/andes-vector-builtins-bases.h: New file.
* config/riscv/andes-vector-builtins-functions.def: New file.
* config/riscv/andes_vector.h: New file.
* config/riscv/andes_vector.md: New file.
* config/riscv/vector.md: Include andes_vector.md.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.exp: Add regression for xandesvector.
*
gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfncvtbf16s.c:
New test.
*
gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfwcvtsbf16.c:
New test.
*
gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfncvtbf16s.c: New
test.
*
gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfwcvtsbf16.c: New
test.
*
gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfncvtbf16s.c: New
test.
*
gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfwcvtsbf16.c: New
test.
*
gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfncvtbf16s.c: New test.
*
gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfwcvtsbf16.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config.gcc | 4 +-
.../riscv/andes-vector-builtins-bases.cc | 97 +++++++++++++++++++
.../riscv/andes-vector-builtins-bases.h | 34 +++++++
.../riscv/andes-vector-builtins-functions.def | 46 +++++++++
gcc/config/riscv/andes-vector.md | 68 +++++++++++++
gcc/config/riscv/andes_vector.h | 32 ++++++
gcc/config/riscv/generic-vector-ooo.md | 3 +-
.../riscv/riscv-vector-builtins-shapes.cc | 2 +-
gcc/config/riscv/riscv-vector-builtins.cc | 21 ++++
gcc/config/riscv/riscv-vector-builtins.def | 1 +
gcc/config/riscv/riscv-vector-builtins.h | 5 +
gcc/config/riscv/riscv.md | 4 +-
gcc/config/riscv/t-riscv | 15 +++
gcc/config/riscv/vector-iterators.md | 13 +++
gcc/config/riscv/vector.md | 19 ++--
gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 12 +++
.../non-overloaded/nds_vfncvtbf16s.c | 46 +++++++++
.../non-overloaded/nds_vfwcvtsbf16.c | 26 +++++
.../non-policy/overloaded/nds_vfncvtbf16s.c | 46 +++++++++
.../non-policy/overloaded/nds_vfwcvtsbf16.c | 26 +++++
.../policy/non-overloaded/nds_vfncvtbf16s.c | 46 +++++++++
.../policy/non-overloaded/nds_vfwcvtsbf16.c | 26 +++++
.../policy/overloaded/nds_vfncvtbf16s.c | 46 +++++++++
.../policy/overloaded/nds_vfwcvtsbf16.c | 26 +++++
25 files changed, 654 insertions(+), 12 deletions(-)
create mode 100644 gcc/config/riscv/andes-vector-builtins-bases.cc
create mode 100644 gcc/config/riscv/andes-vector-builtins-bases.h
create mode 100644 gcc/config/riscv/andes-vector-builtins-functions.def
create mode 100644 gcc/config/riscv/andes-vector.md
create mode 100644 gcc/config/riscv/andes_vector.h
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfncvtbf16s.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfwcvtsbf16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfncvtbf16s.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfwcvtsbf16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfncvtbf16s.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfwcvtsbf16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfncvtbf16s.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfwcvtsbf16.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 6582c15bae2..5f192181688 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1545,6 +1545,8 @@ static const riscv_extra_ext_flag_table_t
riscv_extra_ext_flag_table[] =
RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_isa_flags, MASK_FULL_V),
RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_isa_flags, MASK_VECTOR),
+ RISCV_EXT_FLAG_ENTRY ("xandesvbfhcvt", x_riscv_vector_elen_flags,
MASK_VECTOR_ELEN_BF_16),
+
{NULL, NULL, NULL, 0}
};
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 04e88cce00d..9da9ac51ecc 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,10 +549,10 @@ riscv*)
cpu_type=riscv
extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o
riscv-shorten-memrefs.o riscv-selftests.o riscv-string.o"
extra_objs="${extra_objs} riscv-v.o riscv-vsetvl.o riscv-vector-costs.o
riscv-avlprop.o riscv-vect-permconst.o"
- extra_objs="${extra_objs} riscv-vector-builtins.o
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o
sifive-vector-builtins-bases.o"
+ extra_objs="${extra_objs} riscv-vector-builtins.o
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o
sifive-vector-builtins-bases.o andes-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o riscv-zicfilp.o"
d_target_objs="riscv-d.o"
- extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h
riscv_th_vector.h sifive_vector.h"
+ extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h
riscv_th_vector.h sifive_vector.h andes_vector.h"
target_gtfiles="$target_gtfiles
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
extra_options="${extra_options} riscv/riscv-ext.opt"
diff --git a/gcc/config/riscv/andes-vector-builtins-bases.cc
b/gcc/config/riscv/andes-vector-builtins-bases.cc
new file mode 100644
index 00000000000..8fae29b1bf6
--- /dev/null
+++ b/gcc/config/riscv/andes-vector-builtins-bases.cc
@@ -0,0 +1,97 @@
+/* function_base implementation for Andes custom 'V' Extension for GNU
compiler.
+ Copyright (C) 2024-2025 Free Software Foundation, Inc.
+ Contributed by Andes.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "rtl.h"
+#include "tm_p.h"
+#include "memmodel.h"
+#include "insn-codes.h"
+#include "optabs.h"
+#include "recog.h"
+#include "expr.h"
+#include "basic-block.h"
+#include "function.h"
+#include "fold-const.h"
+#include "gimple.h"
+#include "gimple-iterator.h"
+#include "gimplify.h"
+#include "explow.h"
+#include "emit-rtl.h"
+#include "tree-vector-builder.h"
+#include "rtx-vector-builder.h"
+#include "riscv-vector-builtins.h"
+#include "riscv-vector-builtins-shapes.h"
+#include "andes-vector-builtins-bases.h"
+#include "riscv-vector-builtins-bases.h"
+
+using namespace riscv_vector;
+
+namespace riscv_vector {
+
+/* Implements Andes vfwcvt. */
+template <enum frm_op_type FRM_OP = NO_FRM>
+class nds_vfncvtbf16_f : public function_base
+{
+public:
+ bool apply_mask_policy_p () const override { return false; }
+ bool use_mask_predication_p () const override { return false; }
+ bool has_rounding_mode_operand_p () const override
+ {
+ return FRM_OP == HAS_FRM;
+ }
+ bool may_require_frm_p () const override { return true; }
+
+ rtx expand (function_expander &e) const override
+ {
+ return e.use_exact_insn (code_for_pred_nds_vfncvt_bf16
+ (e.vector_mode ()));
+ }
+};
+
+class nds_vfwcvtbf16_f : public function_base
+{
+public:
+ bool apply_mask_policy_p () const override { return false; }
+ bool use_mask_predication_p () const override { return false; }
+
+ rtx expand (function_expander &e) const override
+ {
+ return e.use_exact_insn (code_for_pred_nds_vfwcvt_bf16 (e.vector_mode ()));
+ }
+};
+
+static CONSTEXPR const nds_vfwcvtbf16_f nds_vfwcvt_s_obj;
+static CONSTEXPR const nds_vfncvtbf16_f<NO_FRM> nds_vfncvt_bf16_obj;
+static CONSTEXPR const nds_vfncvtbf16_f<HAS_FRM> nds_vfncvt_bf16_frm_obj;
+
+/* Declare the function base NAME, pointing it to an instance
+ of class <NAME>_obj. */
+#define BASE(NAME) \
+ namespace bases { const function_base *const NAME = &NAME##_obj; }
+
+BASE (nds_vfwcvt_s)
+BASE (nds_vfncvt_bf16)
+BASE (nds_vfncvt_bf16_frm)
+
+} // end namespace riscv_vector
diff --git a/gcc/config/riscv/andes-vector-builtins-bases.h
b/gcc/config/riscv/andes-vector-builtins-bases.h
new file mode 100644
index 00000000000..61e233034b6
--- /dev/null
+++ b/gcc/config/riscv/andes-vector-builtins-bases.h
@@ -0,0 +1,34 @@
+/* function_base declaration for Andes custom 'V' Extension for GNU compiler.
+ Copyright (C) 2024-2025 Free Software Foundation, Inc.
+ Contributed by Andes.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef GCC_ANDES_VECTOR_BUILTINS_BASES_H
+#define GCC_ANDES_VECTOR_BUILTINS_BASES_H
+
+namespace riscv_vector {
+
+namespace bases {
+extern const function_base *const nds_vfwcvt_s;
+extern const function_base *const nds_vfncvt_bf16;
+extern const function_base *const nds_vfncvt_bf16_frm;
+}
+
+} // end namespace riscv_vector
+
+#endif
diff --git a/gcc/config/riscv/andes-vector-builtins-functions.def
b/gcc/config/riscv/andes-vector-builtins-functions.def
new file mode 100644
index 00000000000..6311c1c8aa0
--- /dev/null
+++ b/gcc/config/riscv/andes-vector-builtins-functions.def
@@ -0,0 +1,46 @@
+/* Intrinsic define macros for Andes custom 'V' Extension for GNU compiler.
+ Copyright (C) 2024-2025 Free Software Foundation, Inc.
+ Contributed by Andes.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+/* Use "DEF_RVV_FUNCTION" macro to define RVV intrinsic functions.
+
+ - NAME not only describes the base_name of the functions
+ but also point to the name of the function_base class.
+
+ - SHAPE point to the function_shape class.
+
+ - PREDS describes the predication types that are supported in the
+ functions.
+
+ - OPS_INFO describes all information of return type and each
+ argument type.
+
+*/
+#ifndef DEF_RVV_FUNCTION
+#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO)
+#endif
+
+/* Andes Vector Packed FP16 Extension (XAndesVBFHCvt). */
+#define REQUIRED_EXTENSIONS XANDESVBFHCVT_EXT
+DEF_RVV_FUNCTION (nds_vfwcvt_s, alu, none_tu_preds, bf16_to_f32_wf_v_ops)
+DEF_RVV_FUNCTION (nds_vfncvt_bf16, narrow_alu, none_tu_preds,
f32_to_bf16_nf_w_ops)
+DEF_RVV_FUNCTION (nds_vfncvt_bf16_frm, narrow_alu_frm, none_tu_preds,
f32_to_bf16_nf_w_ops)
+#undef REQUIRED_EXTENSIONS
+
+#undef DEF_RVV_FUNCTION
diff --git a/gcc/config/riscv/andes-vector.md b/gcc/config/riscv/andes-vector.md
new file mode 100644
index 00000000000..c4812e8535b
--- /dev/null
+++ b/gcc/config/riscv/andes-vector.md
@@ -0,0 +1,68 @@
+;; Machine description for Andes vendor extensions
+;; Copyright (C) 2021-2025 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_c_enum "unspec" [
+ UNSPEC_NDS_VFWCVTBF16
+ UNSPEC_NDS_VFNCVTBF16
+])
+
+;; ....................
+;;
+;; VECTOR BFLOAT16 CONVERSION
+;;
+;; ....................
+
+;; Xandesvbfhcvt extension
+(define_insn "@pred_nds_vfncvt_bf16<mode>"
+ [(set (match_operand:<NDS_V_DOUBLE_TRUNC_BF> 0 "register_operand" "=&vr,
&vr")
+ (if_then_else:<NDS_V_DOUBLE_TRUNC_BF>
+ (unspec:<VM>
+ [(match_operand 3 "vector_length_operand" " rK, rK")
+ (match_operand 4 "const_int_operand" " i, i")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_NDS_VFWCVTBF16)
+ (float_truncate:<NDS_V_DOUBLE_TRUNC_BF>
+ (match_operand:NDS_VWEXTBF 2 "register_operand" "vr,
vr"))
+ (match_operand:<NDS_V_DOUBLE_TRUNC_BF> 1 "vector_merge_operand" "vu,
0")))]
+ "TARGET_VECTOR && TARGET_XANDESVBFHCVT"
+ "nds.vfncvt.bf16.s\t%0,%2"
+ [(set_attr "type" "nds_vfncvtbf16")
+ (set_attr "mode" "<NDS_V_DOUBLE_TRUNC_BF>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[6])"))])
+
+(define_insn "@pred_nds_vfwcvt_bf16<mode>"
+ [(set (match_operand:NDS_VWEXTBF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:NDS_VWEXTBF
+ (unspec_volatile:<VM>
+ [(match_operand 3 "vector_length_operand" " rK, rK")
+ (match_operand 4 "const_int_operand" " i, i")
+ (match_operand 5 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_NDS_VFNCVTBF16)
+ (float_extend:NDS_VWEXTBF
+ (match_operand:<NDS_V_DOUBLE_TRUNC_BF> 2 "register_operand" "vr,
vr"))
+ (match_operand:NDS_VWEXTBF 1 "vector_merge_operand" "vu,
0")))]
+ "TARGET_VECTOR && TARGET_XANDESVBFHCVT"
+ "nds.vfwcvt.s.bf16\t%0,%2"
+ [(set_attr "type" "nds_vfwcvtbf16")
+ (set_attr "mode" "<NDS_V_DOUBLE_TRUNC_BF>")])
diff --git a/gcc/config/riscv/andes_vector.h b/gcc/config/riscv/andes_vector.h
new file mode 100644
index 00000000000..68a620230aa
--- /dev/null
+++ b/gcc/config/riscv/andes_vector.h
@@ -0,0 +1,32 @@
+/* Andes Vector Extension intrinsics include file.
+ Copyright (C) 2025 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef __ANDES_VECTOR_H
+#define __ANDES_VECTOR_H
+
+/* TODO: This should have a separate pragma to include only the Andes
+ vector intrinsics. For now, we are including riscv_vector.h. */
+#include <riscv_vector.h>
+
+#endif // __ANDES_VECTOR_H
diff --git a/gcc/config/riscv/generic-vector-ooo.md
b/gcc/config/riscv/generic-vector-ooo.md
index 773003b49ae..bceda8a65e2 100644
--- a/gcc/config/riscv/generic-vector-ooo.md
+++ b/gcc/config/riscv/generic-vector-ooo.md
@@ -61,7 +61,8 @@
(and (eq_attr "tune" "generic_ooo,generic")
(eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\
vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
- vfncvtftoi,vfncvtftof,vfncvtbf16,vfwcvtbf16"))
+ vfncvtftoi,vfncvtftof,vfncvtbf16,vfwcvtbf16,\
+ nds_vfwcvtbf16,nds_vfncvtbf16"))
"vxu_ooo_issue,vxu_ooo_alu")
;; Vector integer multiplication.
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index 9832eb9e3d1..af07fc571db 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -127,7 +127,7 @@ build_all (function_builder &b, const function_group_info
&group)
static CONSTEXPR const DEF##_def VAR##_obj; \
namespace shapes { const function_shape *const VAR = &VAR##_obj; }
-#define BASE_NAME_MAX_LEN 17
+#define BASE_NAME_MAX_LEN 20
/* Base class for build. */
struct build_base : public function_shape
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 0db7549fc5c..5a9f22d238c 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -52,6 +52,7 @@
#include "riscv-vector-builtins-shapes.h"
#include "riscv-vector-builtins-bases.h"
#include "sifive-vector-builtins-bases.h"
+#include "andes-vector-builtins-bases.h"
using namespace riscv_vector;
@@ -3080,6 +3081,22 @@ static CONSTEXPR const rvv_op_info
all_v_scalar_ptr_index_ops
rvv_arg_type_info (RVV_BASE_void), /* Return type */
scalar_ptr_index_args /* Args */};
+/* A static operand information for vector_type func (vector_type)
+ * function registration. */
+static CONSTEXPR const rvv_op_info f32_to_bf16_nf_w_ops
+ = {f32_ops, /* Types */
+ OP_TYPE_s, /* Suffix
*/
+ rvv_arg_type_info (RVV_BASE_double_trunc_bfloat_vector), /* Return type */
+ v_args /* Args */};
+
+/* A static operand information for vector_type func (vector_type)
+ * function registration. */
+static CONSTEXPR const rvv_op_info bf16_to_f32_wf_v_ops
+ = {f32_ops, /* Types */
+ OP_TYPE_bf16, /* Suffix */
+ rvv_arg_type_info (RVV_BASE_vector), /* Return type */
+ bf_w_v_args /* Args */};
+
/* A static operand information for vector_type func (vector_type).
Some insns just supports SEW=32, such as the crypto vector Zvkg extension.
* function registration. */
@@ -3449,6 +3466,10 @@ static function_group_info function_groups[] = {
#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO)
\
{#NAME, &bases::NAME, &shapes::SHAPE, PREDS, OPS_INFO, REQUIRED_EXTENSIONS},
#include "sifive-vector-builtins-functions.def"
+#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO)
\
+ {#NAME, &bases::NAME, &shapes::SHAPE, PREDS, OPS_INFO, REQUIRED_EXTENSIONS},
+#include "andes-vector-builtins-functions.def"
+
};
/* The RVV types, with their built-in
diff --git a/gcc/config/riscv/riscv-vector-builtins.def
b/gcc/config/riscv/riscv-vector-builtins.def
index be3fb1af816..17de28414f5 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -663,6 +663,7 @@ DEF_RVV_OP_TYPE (v_vvw)
DEF_RVV_OP_TYPE (v_xvw)
DEF_RVV_OP_TYPE (v_ivw)
DEF_RVV_OP_TYPE (v_fvw)
+DEF_RVV_OP_TYPE (bf16)
DEF_RVV_PRED_TYPE (ta)
DEF_RVV_PRED_TYPE (tu)
diff --git a/gcc/config/riscv/riscv-vector-builtins.h
b/gcc/config/riscv/riscv-vector-builtins.h
index 86d81154db9..b52c86695b7 100644
--- a/gcc/config/riscv/riscv-vector-builtins.h
+++ b/gcc/config/riscv/riscv-vector-builtins.h
@@ -131,6 +131,7 @@ enum required_ext
XSFVQMACCDOD_EXT, /* XSFVQMACCDOD extension */
XSFVFNRCLIPXFQF_EXT, /* XSFVFNRCLIPXFQF extension */
XSFVCP_EXT, /* XSFVCP extension*/
+ XANDESVBFHCVT_EXT, /* XANDESVBFHCVT extension */
/* Please update below to isa_name func when add or remove enum type(s). */
};
@@ -172,6 +173,8 @@ static inline const char * required_ext_to_isa_name (enum
required_ext required)
return "xsfvfnrclipxfqf";
case XSFVCP_EXT:
return "xsfvcp";
+ case XANDESVBFHCVT_EXT:
+ return "xandesvbfhcvt";
default:
gcc_unreachable ();
}
@@ -217,6 +220,8 @@ static inline bool required_extensions_specified (enum
required_ext required)
return TARGET_XSFVFNRCLIPXFQF;
case XSFVCP_EXT:
return TARGET_XSFVCP;
+ case XANDESVBFHCVT_EXT:
+ return TARGET_XANDESVBFHCVT;
default:
gcc_unreachable ();
}
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 045528911e6..6deb0514481 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -497,6 +497,8 @@
;; sf_vfnrclip vector fp32 to int8 ranged clip instructions
;; sf_vc vector coprocessor interface without side effect
;; sf_vc_se vector coprocessor interface with side effect
+;; nds_vfwcvtbf16 xandes vector widening brain floating-point to single
floating-point instruction
+;; nds_vfncvtbf16 xandes vector widening brain floating-point to single
floating-point instruction
(define_attr "type"
"unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore,
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
@@ -519,7 +521,7 @@
vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll,
vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz,
vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16,
- sf_vc,sf_vc_se"
+ sf_vc,sf_vc_se,nds_vfwcvtbf16,nds_vfncvtbf16"
(cond [(eq_attr "got" "load") (const_string "load")
;; If a doubleword move uses these expensive instructions,
diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index a1df143f439..d86dc744365 100644
--- a/gcc/config/riscv/t-riscv
+++ b/gcc/config/riscv/t-riscv
@@ -3,6 +3,7 @@ RISCV_BUILTINS_H =
$(srcdir)/config/riscv/riscv-vector-builtins.h \
$(srcdir)/config/riscv/riscv-vector-builtins-functions.def \
$(srcdir)/config/riscv/thead-vector-builtins-functions.def \
$(srcdir)/config/riscv/sifive-vector-builtins-functions.def \
+ $(srcdir)/config/riscv/andes-vector-builtins-functions.def \
riscv-vector-type-indexer.gen.def
riscv-builtins.o: $(srcdir)/config/riscv/riscv-builtins.cc $(CONFIG_H) \
@@ -26,6 +27,7 @@ riscv-vector-builtins.o:
$(srcdir)/config/riscv/riscv-vector-builtins.cc \
$(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \
$(srcdir)/config/riscv/riscv-vector-builtins-bases.h \
$(srcdir)/config/riscv/sifive-vector-builtins-bases.h \
+ $(srcdir)/config/riscv/andes-vector-builtins-bases.h \
$(srcdir)/config/riscv/riscv-vector-builtins-types.def \
$(srcdir)/config/riscv/sifive-vector-builtins-functions.def \
$(RISCV_BUILTINS_H)
@@ -69,6 +71,19 @@ sifive-vector-builtins-bases.o: \
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/riscv/sifive-vector-builtins-bases.cc
+andes-vector-builtins-bases.o: \
+ $(srcdir)/config/riscv/andes-vector-builtins-bases.cc \
+ $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \
+ $(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) $(RECOG_H) \
+ $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) fold-const.h $(GIMPLE_H) \
+ gimple-iterator.h gimplify.h explow.h $(EMIT_RTL_H) tree-vector-builder.h \
+ rtx-vector-builder.h \
+ $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \
+ $(srcdir)/config/riscv/andes-vector-builtins-bases.h \
+ $(RISCV_BUILTINS_H)
+ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
+ $(srcdir)/config/riscv/andes-vector-builtins-bases.cc
+
riscv-sr.o: $(srcdir)/config/riscv/riscv-sr.cc $(CONFIG_H) \
$(SYSTEM_H) $(TM_H)
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index db89b3609b1..5d09af1ea87 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4987,3 +4987,16 @@
(RVVM4HI "HF") (RVVM2HI "HF") (RVVM1HI "HF") (RVVMF2HI "HF") (RVVMF4HI "HF")
(RVVM4SI "SF") (RVVM2SI "SF") (RVVM1SI "SF") (RVVMF2SI "SF")
])
+
+(define_mode_iterator NDS_VWEXTBF [
+ (RVVM8SF "TARGET_VECTOR_ELEN_FP_32")
+ (RVVM4SF "TARGET_VECTOR_ELEN_FP_32")
+ (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
+ (RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
+ (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+])
+
+(define_mode_attr NDS_V_DOUBLE_TRUNC_BF [
+ (RVVM8SF "RVVM4BF") (RVVM4SF "RVVM2BF") (RVVM2SF "RVVM1BF")
+ (RVVM1SF "RVVMF2BF") (RVVMF2SF "RVVMF4BF")
+])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index e7ffeeb9cd6..e71d386f150 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -56,7 +56,8 @@
vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,\
vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\
-
vfncvtbf16,vfwcvtbf16,vfwmaccbf16,sf_vqmacc,sf_vfnrclip,sf_vc,sf_vc_se")
+
vfncvtbf16,vfwcvtbf16,vfwmaccbf16,sf_vqmacc,sf_vfnrclip,sf_vc,sf_vc_se,\
+ nds_vfwcvtbf16,nds_vfncvtbf16")
(const_string "true")]
(const_string "false")))
@@ -81,7 +82,7 @@
vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,\
vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\
- vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
+
vfncvtbf16,vfwcvtbf16,vfwmaccbf16,nds_vfwcvtbf16,nds_vfncvtbf16")
(const_string "true")]
(const_string "false")))
@@ -488,7 +489,8 @@
vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,vror,vwsll,\
vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,\
- vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
+ vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16,\
+ nds_vfwcvtbf16,nds_vfncvtbf16")
(const_int INVALID_ATTRIBUTE)
(and (eq_attr "type" "vlde,vste,vlsegde,vssegte,vlsegds,vssegts,\
vlsegdff,vssegtux,vlsegdox,vlsegdux")
@@ -801,7 +803,8 @@
(const_int 2)
(eq_attr "type"
"vimerge,vfmerge,vcompress,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
-
vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c")
+
vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\
+ nds_vfwcvtbf16,nds_vfncvtbf16")
(const_int 1)
(eq_attr "type" "vimuladd,vfmuladd")
@@ -865,7 +868,7 @@
(const_int 6)
(eq_attr "type"
"vmpop,vmffs,vmidx,vssegte,vcpop,vclz,vctz,vgmul,vaesef,vaesem,vaesdf,\
- vaesdm,vaesz,vsm4r")
+ vaesdm,vaesz,vsm4r,nds_vfwcvtbf16,nds_vfncvtbf16")
(const_int 3)]
(const_int INVALID_ATTRIBUTE)))
@@ -899,7 +902,8 @@
(eq_attr "type" "vimuladd,vfmuladd")
(symbol_ref "riscv_vector::get_ta(operands[7])")
- (eq_attr "type" "vmidx,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaesz,vsm4r")
+ (eq_attr "type" "vmidx,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaesz,vsm4r,\
+ nds_vfwcvtbf16,nds_vfncvtbf16")
(symbol_ref "riscv_vector::get_ta(operands[4])")]
(const_int INVALID_ATTRIBUTE)))
@@ -944,7 +948,7 @@
vfncvtbf16,vfwcvtbf16")
(const_int 7)
(eq_attr "type"
"vldm,vstm,vmalu,vmalu,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaesz,\
- vsm4r")
+ vsm4r,nds_vfwcvtbf16,nds_vfncvtbf16")
(const_int 5)
;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
@@ -8938,3 +8942,4 @@
(include "autovec.md")
(include "autovec-opt.md")
(include "sifive-vector.md")
+(include "andes-vector.md")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index d76a2d7fe74..877cc55bb88 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -43,6 +43,8 @@ dg-runtest [lsort [glob -nocomplain
$srcdir/$subdir/xsfvector/*.\[cS\]]] \
"" $CFLAGS
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xtheadvector/*.\[cS\]]] \
"" $CFLAGS
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xandesvector/*.\[cS\]]] \
+ "" $CFLAGS
gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
"" $CFLAGS
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \
@@ -149,5 +151,15 @@ foreach op $AUTOVEC_TEST_OPTS {
"$op" ""
}
+set POLICY [list {policy} {non-policy} ]
+set OVERLOAD [list {overloaded} {non-overloaded} ]
+foreach po $POLICY {
+ foreach ov $OVERLOAD {
+ # For Andes Vector feature tests
+ dg-runtest [lsort [glob -nocomplain
$srcdir/$subdir/xandesvector/$po/$ov/*.\[cS\]]] \
+ "" $CFLAGS
+ }
+}
+
# All done.
dg-finish
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfncvtbf16s.c
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfncvtbf16s.c
new file mode 100644
index 00000000000..f1c66acca00
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfncvtbf16s.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gv_xandesvbfhcvt -mabi=ilp32 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv32 } } } */
+/* { dg-options "-march=rv64gv_xandesvbfhcvt -mabi=lp64 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv64 } } } */
+
+#include <andes_vector.h>
+
+vbfloat16mf4_t test_nds_vfncvt_bf16_s_bf16mf4(vfloat32mf2_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16mf4(vs2, vl);
+}
+
+vbfloat16mf2_t test_nds_vfncvt_bf16_s_bf16mf2(vfloat32m1_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16mf2(vs2, vl);
+}
+
+vbfloat16m1_t test_nds_vfncvt_bf16_s_bf16m1(vfloat32m2_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16m1(vs2, vl);
+}
+
+vbfloat16m2_t test_nds_vfncvt_bf16_s_bf16m2(vfloat32m4_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16m2(vs2, vl);
+}
+
+vbfloat16m4_t test_nds_vfncvt_bf16_s_bf16m4(vfloat32m8_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16m4(vs2, vl);
+}
+
+vbfloat16mf4_t test_nds_vfncvt_bf16_s_bf16mf4_rm(vfloat32mf2_t vs2, size_t vl)
{
+ return __riscv_nds_vfncvt_bf16_s_bf16mf4_rm(vs2, __RISCV_FRM_RNE, vl);
+}
+
+vbfloat16mf2_t test_nds_vfncvt_bf16_s_bf16mf2_rm(vfloat32m1_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16mf2_rm(vs2, __RISCV_FRM_RNE, vl);
+}
+
+vbfloat16m1_t test_nds_vfncvt_bf16_s_bf16m1_rm(vfloat32m2_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16m1_rm(vs2, __RISCV_FRM_RNE, vl);
+}
+
+vbfloat16m2_t test_nds_vfncvt_bf16_s_bf16m2_rm(vfloat32m4_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16m2_rm(vs2, __RISCV_FRM_RNE, vl);
+}
+
+vbfloat16m4_t test_nds_vfncvt_bf16_s_bf16m4_rm(vfloat32m8_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16m4_rm(vs2, __RISCV_FRM_RNE, vl);
+}
+/* { dg-final { scan-assembler-times
{vseti?vli\s+[a-z0-9]+,\s*a0,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vmv[1248]r\.v\s+[0-9v,]+\s+nds\.vfncvt\.bf16\.s[ivxfswum.]*\s+}
10 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfwcvtsbf16.c
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfwcvtsbf16.c
new file mode 100644
index 00000000000..4193c6b10ba
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfwcvtsbf16.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gv_xandesvbfhcvt -mabi=ilp32 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv32 } } } */
+/* { dg-options "-march=rv64gv_xandesvbfhcvt -mabi=lp64 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv64 } } } */
+
+#include <andes_vector.h>
+
+vfloat32mf2_t test_nds_vfwcvt_s_bf16_f32mf2(vbfloat16mf4_t vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s_bf16_f32mf2(vs2, vl);
+}
+
+vfloat32m1_t test_nds_vfwcvt_s_bf16_f32m1(vbfloat16mf2_t vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s_bf16_f32m1(vs2, vl);
+}
+
+vfloat32m2_t test_nds_vfwcvt_s_bf16_f32m2(vbfloat16m1_t vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s_bf16_f32m2(vs2, vl);
+}
+
+vfloat32m4_t test_nds_vfwcvt_s_bf16_f32m4(vbfloat16m2_t vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s_bf16_f32m4(vs2, vl);
+}
+
+vfloat32m8_t test_nds_vfwcvt_s_bf16_f32m8(vbfloat16m4_t vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s_bf16_f32m8(vs2, vl);
+}
+/* { dg-final { scan-assembler-times
{vseti?vli\s+[a-z0-9]+,\s*a0,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vmv[1248]r\.v\s+[0-9v,]+\s+nds\.vfwcvt\.s\.bf16[ivxfswum.]*\s+}
5 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfncvtbf16s.c
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfncvtbf16s.c
new file mode 100644
index 00000000000..838bea77a62
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfncvtbf16s.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gv_xandesvbfhcvt -mabi=ilp32 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv32 } } } */
+/* { dg-options "-march=rv64gv_xandesvbfhcvt -mabi=lp64 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv64 } } } */
+
+#include <andes_vector.h>
+
+vbfloat16mf4_t test_nds_vfncvt_bf16_s_bf16mf4(vfloat32mf2_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16(vs2, vl);
+}
+
+vbfloat16mf2_t test_nds_vfncvt_bf16_s_bf16mf2(vfloat32m1_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16(vs2, vl);
+}
+
+vbfloat16m1_t test_nds_vfncvt_bf16_s_bf16m1(vfloat32m2_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16(vs2, vl);
+}
+
+vbfloat16m2_t test_nds_vfncvt_bf16_s_bf16m2(vfloat32m4_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16(vs2, vl);
+}
+
+vbfloat16m4_t test_nds_vfncvt_bf16_s_bf16m4(vfloat32m8_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16(vs2, vl);
+}
+
+vbfloat16mf4_t test_nds_vfncvt_bf16_s_bf16mf4_rm(vfloat32mf2_t vs2, size_t vl)
{
+ return __riscv_nds_vfncvt_bf16(vs2, __RISCV_FRM_RNE, vl);
+}
+
+vbfloat16mf2_t test_nds_vfncvt_bf16_s_bf16mf2_rm(vfloat32m1_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16(vs2, __RISCV_FRM_RNE, vl);
+}
+
+vbfloat16m1_t test_nds_vfncvt_bf16_s_bf16m1_rm(vfloat32m2_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16(vs2, __RISCV_FRM_RNE, vl);
+}
+
+vbfloat16m2_t test_nds_vfncvt_bf16_s_bf16m2_rm(vfloat32m4_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16(vs2, __RISCV_FRM_RNE, vl);
+}
+
+vbfloat16m4_t test_nds_vfncvt_bf16_s_bf16m4_rm(vfloat32m8_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16(vs2, __RISCV_FRM_RNE, vl);
+}
+/* { dg-final { scan-assembler-times
{vseti?vli\s+[a-z0-9]+,\s*a0,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vmv[1248]r\.v\s+[0-9v,]+\s+nds\.vfncvt\.bf16\.s[ivxfswum.]*\s+}
10 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfwcvtsbf16.c
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfwcvtsbf16.c
new file mode 100644
index 00000000000..0a09916e47f
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfwcvtsbf16.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gv_xandesvbfhcvt -mabi=ilp32 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv32 } } } */
+/* { dg-options "-march=rv64gv_xandesvbfhcvt -mabi=lp64 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv64 } } } */
+
+#include <andes_vector.h>
+
+vfloat32mf2_t test_nds_vfwcvt_s_bf16_f32mf2(vbfloat16mf4_t vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s(vs2, vl);
+}
+
+vfloat32m1_t test_nds_vfwcvt_s_bf16_f32m1(vbfloat16mf2_t vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s(vs2, vl);
+}
+
+vfloat32m2_t test_nds_vfwcvt_s_bf16_f32m2(vbfloat16m1_t vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s(vs2, vl);
+}
+
+vfloat32m4_t test_nds_vfwcvt_s_bf16_f32m4(vbfloat16m2_t vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s(vs2, vl);
+}
+
+vfloat32m8_t test_nds_vfwcvt_s_bf16_f32m8(vbfloat16m4_t vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s(vs2, vl);
+}
+/* { dg-final { scan-assembler-times
{vseti?vli\s+[a-z0-9]+,\s*a0,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vmv[1248]r\.v\s+[0-9v,]+\s+nds\.vfwcvt\.s\.bf16[ivxfswum.]*\s+}
5 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfncvtbf16s.c
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfncvtbf16s.c
new file mode 100644
index 00000000000..29a0d681c7d
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfncvtbf16s.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gv_xandesvbfhcvt -mabi=ilp32 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv32 } } } */
+/* { dg-options "-march=rv64gv_xandesvbfhcvt -mabi=lp64 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv64 } } } */
+
+#include <andes_vector.h>
+
+vbfloat16mf4_t test_nds_vfncvt_bf16_s_bf16mf4_tu(vbfloat16mf4_t vd,
vfloat32mf2_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16mf4_tu(vd, vs2, vl);
+}
+
+vbfloat16mf2_t test_nds_vfncvt_bf16_s_bf16mf2_tu(vbfloat16mf2_t vd,
vfloat32m1_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16mf2_tu(vd, vs2, vl);
+}
+
+vbfloat16m1_t test_nds_vfncvt_bf16_s_bf16m1_tu(vbfloat16m1_t vd, vfloat32m2_t
vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16m1_tu(vd, vs2, vl);
+}
+
+vbfloat16m2_t test_nds_vfncvt_bf16_s_bf16m2_tu(vbfloat16m2_t vd, vfloat32m4_t
vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16m2_tu(vd, vs2, vl);
+}
+
+vbfloat16m4_t test_nds_vfncvt_bf16_s_bf16m4_tu(vbfloat16m4_t vd, vfloat32m8_t
vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16m4_tu(vd, vs2, vl);
+}
+
+vbfloat16mf4_t test_nds_vfncvt_bf16_s_bf16mf4_rm_tu(vbfloat16mf4_t vd,
vfloat32mf2_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16mf4_rm_tu(vd, vs2, __RISCV_FRM_RNE,
vl);
+}
+
+vbfloat16mf2_t test_nds_vfncvt_bf16_s_bf16mf2_rm_tu(vbfloat16mf2_t vd,
vfloat32m1_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16mf2_rm_tu(vd, vs2, __RISCV_FRM_RNE,
vl);
+}
+
+vbfloat16m1_t test_nds_vfncvt_bf16_s_bf16m1_rm_tu(vbfloat16m1_t vd,
vfloat32m2_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16m1_rm_tu(vd, vs2, __RISCV_FRM_RNE,
vl);
+}
+
+vbfloat16m2_t test_nds_vfncvt_bf16_s_bf16m2_rm_tu(vbfloat16m2_t vd,
vfloat32m4_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16m2_rm_tu(vd, vs2, __RISCV_FRM_RNE,
vl);
+}
+
+vbfloat16m4_t test_nds_vfncvt_bf16_s_bf16m4_rm_tu(vbfloat16m4_t vd,
vfloat32m8_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_s_bf16m4_rm_tu(vd, vs2, __RISCV_FRM_RNE,
vl);
+}
+/* { dg-final { scan-assembler-times
{vseti?vli\s+[a-z0-9]+,\s*a0,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+nds\.vfncvt\.bf16\.s[ivxfswum.]*\s+}
10 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfwcvtsbf16.c
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfwcvtsbf16.c
new file mode 100644
index 00000000000..8d206435a0b
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfwcvtsbf16.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gv_xandesvbfhcvt -mabi=ilp32 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv32 } } } */
+/* { dg-options "-march=rv64gv_xandesvbfhcvt -mabi=lp64 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv64 } } } */
+
+#include <andes_vector.h>
+
+vfloat32mf2_t test_nds_vfwcvt_s_bf16_f32mf2_tu(vfloat32mf2_t vd,
vbfloat16mf4_t vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s_tu(vd, vs2, vl);
+}
+
+vfloat32m1_t test_nds_vfwcvt_s_bf16_f32m1_tu(vfloat32m1_t vd, vbfloat16mf2_t
vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s_tu(vd, vs2, vl);
+}
+
+vfloat32m2_t test_nds_vfwcvt_s_bf16_f32m2_tu(vfloat32m2_t vd, vbfloat16m1_t
vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s_tu(vd, vs2, vl);
+}
+
+vfloat32m4_t test_nds_vfwcvt_s_bf16_f32m4_tu(vfloat32m4_t vd, vbfloat16m2_t
vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s_tu(vd, vs2, vl);
+}
+
+vfloat32m8_t test_nds_vfwcvt_s_bf16_f32m8_tu(vfloat32m8_t vd, vbfloat16m4_t
vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s_tu(vd, vs2, vl);
+}
+/* { dg-final { scan-assembler-times
{vseti?vli\s+[a-z0-9]+,\s*a0,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+nds\.vfwcvt\.s\.bf16[ivxfswum.]*\s+}
5 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfncvtbf16s.c
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfncvtbf16s.c
new file mode 100644
index 00000000000..a9f77ed2e5b
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfncvtbf16s.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gv_xandesvbfhcvt -mabi=ilp32 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv32 } } } */
+/* { dg-options "-march=rv64gv_xandesvbfhcvt -mabi=lp64 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv64 } } } */
+
+#include <andes_vector.h>
+
+vbfloat16mf4_t test_nds_vfncvt_bf16_s_bf16mf4_tu(vbfloat16mf4_t vd,
vfloat32mf2_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_tu(vd, vs2, vl);
+}
+
+vbfloat16mf2_t test_nds_vfncvt_bf16_s_bf16mf2_tu(vbfloat16mf2_t vd,
vfloat32m1_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_tu(vd, vs2, vl);
+}
+
+vbfloat16m1_t test_nds_vfncvt_bf16_s_bf16m1_tu(vbfloat16m1_t vd, vfloat32m2_t
vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_tu(vd, vs2, vl);
+}
+
+vbfloat16m2_t test_nds_vfncvt_bf16_s_bf16m2_tu(vbfloat16m2_t vd, vfloat32m4_t
vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_tu(vd, vs2, vl);
+}
+
+vbfloat16m4_t test_nds_vfncvt_bf16_s_bf16m4_tu(vbfloat16m4_t vd, vfloat32m8_t
vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_tu(vd, vs2, vl);
+}
+
+vbfloat16mf4_t test_nds_vfncvt_bf16_s_bf16mf4_rm_tu(vbfloat16mf4_t vd,
vfloat32mf2_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_tu(vd, vs2, __RISCV_FRM_RNE, vl);
+}
+
+vbfloat16mf2_t test_nds_vfncvt_bf16_s_bf16mf2_rm_tu(vbfloat16mf2_t vd,
vfloat32m1_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_tu(vd, vs2, __RISCV_FRM_RNE, vl);
+}
+
+vbfloat16m1_t test_nds_vfncvt_bf16_s_bf16m1_rm_tu(vbfloat16m1_t vd,
vfloat32m2_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_tu(vd, vs2, __RISCV_FRM_RNE, vl);
+}
+
+vbfloat16m2_t test_nds_vfncvt_bf16_s_bf16m2_rm_tu(vbfloat16m2_t vd,
vfloat32m4_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_tu(vd, vs2, __RISCV_FRM_RNE, vl);
+}
+
+vbfloat16m4_t test_nds_vfncvt_bf16_s_bf16m4_rm_tu(vbfloat16m4_t vd,
vfloat32m8_t vs2, size_t vl) {
+ return __riscv_nds_vfncvt_bf16_tu(vd, vs2, __RISCV_FRM_RNE, vl);
+}
+/* { dg-final { scan-assembler-times
{vseti?vli\s+[a-z0-9]+,\s*a0,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+nds\.vfncvt\.bf16\.s[ivxfswum.]*\s+}
10 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfwcvtsbf16.c
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfwcvtsbf16.c
new file mode 100644
index 00000000000..8d206435a0b
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfwcvtsbf16.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gv_xandesvbfhcvt -mabi=ilp32 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv32 } } } */
+/* { dg-options "-march=rv64gv_xandesvbfhcvt -mabi=lp64 -O3
-fno-schedule-insns -fno-schedule-insns2" { target { rv64 } } } */
+
+#include <andes_vector.h>
+
+vfloat32mf2_t test_nds_vfwcvt_s_bf16_f32mf2_tu(vfloat32mf2_t vd,
vbfloat16mf4_t vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s_tu(vd, vs2, vl);
+}
+
+vfloat32m1_t test_nds_vfwcvt_s_bf16_f32m1_tu(vfloat32m1_t vd, vbfloat16mf2_t
vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s_tu(vd, vs2, vl);
+}
+
+vfloat32m2_t test_nds_vfwcvt_s_bf16_f32m2_tu(vfloat32m2_t vd, vbfloat16m1_t
vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s_tu(vd, vs2, vl);
+}
+
+vfloat32m4_t test_nds_vfwcvt_s_bf16_f32m4_tu(vfloat32m4_t vd, vbfloat16m2_t
vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s_tu(vd, vs2, vl);
+}
+
+vfloat32m8_t test_nds_vfwcvt_s_bf16_f32m8_tu(vfloat32m8_t vd, vbfloat16m4_t
vs2, size_t vl) {
+ return __riscv_nds_vfwcvt_s_tu(vd, vs2, vl);
+}
+/* { dg-final { scan-assembler-times
{vseti?vli\s+[a-z0-9]+,\s*a0,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+nds\.vfwcvt\.s\.bf16[ivxfswum.]*\s+}
5 } } */
--
2.34.1
