From: Pan Li <pan2...@intel.com>
Add asm dump check and run test for vec_duplicate + vnmsac.vvm
combine to vnmsac.vx, with the GR2VR cost is 0, 2 and 15.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
for vnmsac.vx.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u8.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
.../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c | 1 +
.../rvv/autovec/vx_vf/vx_vnmsac-run-1-u16.c | 16 ++++++++++++++++
.../rvv/autovec/vx_vf/vx_vnmsac-run-1-u32.c | 16 ++++++++++++++++
.../rvv/autovec/vx_vf/vx_vnmsac-run-1-u64.c | 16 ++++++++++++++++
.../riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u8.c | 16 ++++++++++++++++
16 files changed, 76 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u8.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index 187b681bea2..27204def3ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -23,3 +23,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index a3a785abf06..4c655c52f64 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -23,3 +23,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 4142e1b67ec..27f525308f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
"-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4"
} } } } } */
/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index 5b36f084ac8..8622b30bc5f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -23,3 +23,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vaaddu.vx} 2 } } */
/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index 9c034dcf7c6..330d541d170 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -23,3 +23,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index ce50de69190..7095cc7fc40 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -23,3 +23,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index 5cd6b417092..29824ed80f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -23,3 +23,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index f9d4a63198d..525dd3814be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -23,3 +23,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 2264014e2e2..7c986252285 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -23,3 +23,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 928909386d9..9de7c9f06c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -23,3 +23,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 271b4d62e3f..b35a9b76df0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -23,3 +23,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index f75695b6b5c..9eeb27286a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -23,3 +23,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u16.c
new file mode 100644
index 00000000000..9427fddb6cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T uint16_t
+#define NAME nmsac
+#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+ RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u32.c
new file mode 100644
index 00000000000..da9fc9cf1f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T uint32_t
+#define NAME nmsac
+#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+ RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u64.c
new file mode 100644
index 00000000000..5e4cde410ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T uint64_t
+#define NAME nmsac
+#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+ RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u8.c
new file mode 100644
index 00000000000..ab525808dc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-u8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T uint8_t
+#define NAME nmsac
+#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+ RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"
--
2.43.0
