From: Matthew Fortune <matthew.fort...@imgtec.com>
The compressed MIPS ISAs (microMIPS and MIPS16) require the LSB of
an address to indicate which ISA to execute. The non-conformant
patterns used in these tests cannot set the ISA mode bit and may
attempt to directly call the variable which triggers an error from
the assembler about calling a different ISA mode.
Add documentation for the newly introduced mips_compressed effective
target in doc/sourcebuild.texi. This selector is used to skip tests
that attempt to call variables directly, which is not supported by
compressed MIPS ISAs such as microMIPS and MIPS16.
gcc/doc/
* sourcebuild.texi (mips_compressed): Document new effective
target.
gcc/testsuite/
* gcc.c-torture/compile/20020129-1.c: Skip for MIPS16/microMIPS.
* gcc.c-torture/compile/pr37433-1.c: Likewise.
* gcc.c-torture/compile/pr37433.c: Likewise.
* lib/target-supports.exp
(check_effective_target_mips_compressed): New function.
Cherry-picked 97f2d5c6403c0cb8b65e059349ec18ffc9505bfd
from https://github.com/MIPS/gcc
Signed-off-by: Matthew Fortune <matthew.fort...@imgtec.com>
Signed-off-by: Faraz Shahbazker <fshahbaz...@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.ra...@htecgroup.com>
---
gcc/doc/sourcebuild.texi | 6 ++++++
gcc/testsuite/gcc.c-torture/compile/20020129-1.c | 5 +++++
gcc/testsuite/gcc.c-torture/compile/pr37433-1.c | 5 +++++
gcc/testsuite/gcc.c-torture/compile/pr37433.c | 5 +++++
gcc/testsuite/lib/target-supports.exp | 10 ++++++++++
5 files changed, 31 insertions(+)
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index b7167b39bb8..aee62607cc6 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2393,6 +2393,12 @@ LoongArch binutils supports call36 relocation.
@item mips64
MIPS target supports 64-bit instructions.
+@item mips_compressed
+True if the target is using a compressed MIPS ISA, such as microMIPS or
+MIPS16. These ISAs require the least significant bit of an address to
+indicate the ISA mode, which can cause assembler errors when calling
+variables directly.
+
@item nomips16
MIPS target does not produce MIPS16 code.
diff --git a/gcc/testsuite/gcc.c-torture/compile/20020129-1.c
b/gcc/testsuite/gcc.c-torture/compile/20020129-1.c
index c14ac07655e..d06bcb0976d 100644
--- a/gcc/testsuite/gcc.c-torture/compile/20020129-1.c
+++ b/gcc/testsuite/gcc.c-torture/compile/20020129-1.c
@@ -2,6 +2,11 @@
/* { dg-require-effective-target indirect_calls } */
+/* MIPS compressed ISAs require the LSB of an address to indicate which
+ ISA mode to use. This test cannot do that and raises an assembler
+ warning (binutils 2.29 onwards) of a branch to a different ISA. */
+/* { dg-skip-if "" { mips_compressed } } */
+
typedef struct
{
long long a[10];
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr37433-1.c
b/gcc/testsuite/gcc.c-torture/compile/pr37433-1.c
index 48a57b637d7..5948b3d740a 100644
--- a/gcc/testsuite/gcc.c-torture/compile/pr37433-1.c
+++ b/gcc/testsuite/gcc.c-torture/compile/pr37433-1.c
@@ -1,5 +1,10 @@
/* { dg-require-effective-target indirect_calls } */
+/* MIPS compressed ISAs require the LSB of an address to indicate which
+ ISA mode to use. This test cannot do that and raises an assembler
+ warning (binutils 2.29 onwards) of a branch to a different ISA. */
+/* { dg-skip-if "" { mips_compressed } } */
+
void regex_subst(void)
{
const void *subst = "";
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr37433.c
b/gcc/testsuite/gcc.c-torture/compile/pr37433.c
index 95d168afa2f..69e622132af 100644
--- a/gcc/testsuite/gcc.c-torture/compile/pr37433.c
+++ b/gcc/testsuite/gcc.c-torture/compile/pr37433.c
@@ -1,5 +1,10 @@
/* { dg-require-effective-target indirect_calls } */
+
+/* MIPS compressed ISAs require the LSB of an address to indicate which
+ ISA mode to use. This test cannot do that and raises an assembler
+ warning (binutils 2.29 onwards) of a branch to a different ISA. */
+/* { dg-skip-if "" { mips_compressed } } */
int regex_subst(void)
{
const void *subst = "";
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index fd58682cae3..4f005c5a7d2 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -1514,6 +1514,16 @@ proc check_effective_target_mips64 { } {
}]
}
+# Return true if the target is using a compressed MIPS ISA.
+
+proc check_effective_target_mips_compressed { } {
+ return [check_no_compiler_messages mips_compressed assembly {
+ #if !defined (__mips_micromips) && !defined (__mips16)
+ #error !__mips_micromips && !__mips16
+ #endif
+ }]
+}
+
# Return true if the target is a MIPS target that does not produce
# MIPS16 code.
--
2.34.1
