On Tue, Oct 07, 2025 at 06:55:25PM +0000, Tamar Christina wrote:
> Consider:
>
> #include <arm_sve.h>
>
> svbool_t f8 ()
> {
> return svptrue_b8 ();
> }
>
> svbool_t f16 ()
> {
> return svptrue_b16 ();
> }
>
> The first one has every bit significant, and the second one it's every 2nd
> bit.
> But with DW_AT_bit_stride = 1, I'm not sure how a user in GDB is able to tell
> If the register values belong to a predicate where every other lane is
> inactive
> or one where every entry is active.
DWARF should describe user types, so if svbool_t is always 1-bit size 1-bit
stride, I think you want for that instead of the current
vec: DW_TAG_array_type
DW_AT_name "__SVBool_t"
DW_AT_GNU_vector
DW_AT_type inner
DW_AT_sibling inner
DW_TAG_subrange_type
DW_AT_upper_bound DW_OP_bregx 0x2e 0 DW_OP_lit8 DW_OP_mul DW_OP_lit1
DW_OP_minus
inner: DW_TAG_base_type
DW_AT_byte_size 1
DW_AT_encoding 2
DW_AT_name "__unknown__"
add DW_AT_bit_stride to DW_TAG_array_type and replace DW_AT_byte_size 1 with
DW_AT_bit_size 1 in DW_TAG_base_type.
But I'll stress out this should be done solely for the targets which have
such kind of VECTOR_BOOLEAN_TYPE_Ps, not all because many have other
implementation. And even if aarch64 doesn't have 2/4/8-bit strided bool
vectors (really don't know), it is quite likely RISC-V has those.
Jakub
