[committed GCC 14/15] aarch64: Fix pmsdsfr_el1 encoding

[Alice Carlotti]

The encoding was fixed in Binutils in May 2024, but we didn't copy the
fix to GCC at the time.

Committed as obvious to both the gcc-14 and gcc-15 branches.

gcc/ChangeLog:

        * config/aarch64/aarch64-sys-regs.def: Fix pmsdsfr_el1 encoding.

gcc/testsuite/ChangeLog:

        * gcc.target/aarch64/acle/rwsr-armv8p9.c: Fix pmsdsfr_el1
        encoding.


diff --git a/gcc/config/aarch64/aarch64-sys-regs.def 
b/gcc/config/aarch64/aarch64-sys-regs.def
index 
39e6c5c646fb2f05d6e8186ba3ecd3b9ccfd8bc5..b2f174f25469cfcac3ab1e9dcc82f4b17d953fd5
 100644
--- a/gcc/config/aarch64/aarch64-sys-regs.def
+++ b/gcc/config/aarch64/aarch64-sys-regs.def
@@ -740,7 +740,7 @@
   SYSREG ("pmscr_el1",         CPENC (3,0,9,9,0),      F_ARCHEXT,              
AARCH64_FEATURE (PROFILE))
   SYSREG ("pmscr_el12",                CPENC (3,5,9,9,0),      F_ARCHEXT,      
        AARCH64_FEATURE (PROFILE))
   SYSREG ("pmscr_el2",         CPENC (3,4,9,9,0),      F_ARCHEXT,              
AARCH64_FEATURE (PROFILE))
-  SYSREG ("pmsdsfr_el1",       CPENC (3,4,9,10,4),     F_ARCHEXT,              
AARCH64_FEATURE (SPE_FDS))
+  SYSREG ("pmsdsfr_el1",       CPENC (3,0,9,10,4),     F_ARCHEXT,              
AARCH64_FEATURE (SPE_FDS))
   SYSREG ("pmselr_el0",                CPENC (3,3,9,12,5),     0,              
        AARCH64_NO_FEATURES)
   SYSREG ("pmsevfr_el1",       CPENC (3,0,9,9,5),      F_ARCHEXT,              
AARCH64_FEATURE (PROFILE))
   SYSREG ("pmsfcr_el1",                CPENC (3,0,9,9,4),      F_ARCHEXT,      
        AARCH64_FEATURE (PROFILE))
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c 
b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c
index 
c49fbb5368e07358be6cbd15f88334b55d6d31c9..1ff51de8ffe1a88dfbb229fe46705044db9af0ba
 100644
--- a/gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c
+++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c
@@ -72,7 +72,7 @@ readwrite_armv8p9a_sysregs (long long int a)
   a = __arm_rsr64 ("pmicfiltr_el0"); /* { { dg-final { scan-assembler 
"mrs\tx0, s3_3_c9_c6_0" } } */
   a = __arm_rsr64 ("pmicntr_el0"); /* { { dg-final { scan-assembler "mrs\tx0, 
s3_3_c9_c4_0" } } */
   a = __arm_rsr64 ("pmicntsvr_el1"); /* { { dg-final { scan-assembler 
"mrs\tx0, s2_0_c14_c12_0" } } */
-  a = __arm_rsr64 ("pmsdsfr_el1"); /* { { dg-final { scan-assembler "mrs\tx0, 
s3_4_c9_c10_4" } } */
+  a = __arm_rsr64 ("pmsdsfr_el1"); /* { { dg-final { scan-assembler "mrs\tx0, 
s3_0_c9_c10_4" } } */
   a = __arm_rsr64 ("pmsscr_el1"); /* { { dg-final { scan-assembler "mrs\tx0, 
s3_0_c9_c13_3" } } */
   a = __arm_rsr64 ("pmuacr_el1"); /* { { dg-final { scan-assembler "mrs\tx0, 
s3_0_c9_c14_4" } } */
   a = __arm_rsr64 ("por_el0"); /* { { dg-final { scan-assembler "mrs\tx0, 
s3_3_c10_c2_4" } } */