On 10/15/25 8:29 AM, Aleksa Paunovic wrote:
From: Chao-ying Fu <[email protected]>
Ensure proper alignment for big-endian RISC-V targets.
Signed-off-by: Aleksa Paunovic <[email protected]>
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_subword_address): Add emit_move_insn
for big-endian.
---
gcc/config/riscv/riscv.cc | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index d5de76c34..f3d39785e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -12825,6 +12825,12 @@ riscv_subword_address (rtx mem, rtx *aligned_mem, rtx
*shift, rtx *mask,
/* Calculate the shift amount. */
emit_move_insn (*shift, gen_rtx_AND (SImode, gen_lowpart (SImode, addr),
gen_int_mode (3, SImode)));
+ if (TARGET_BIG_ENDIAN) {
+ emit_move_insn (*shift, gen_rtx_XOR (SImode, *shift,
+ gen_int_mode (GET_MODE (mem) == QImode
+ ? 3 : 2, SImode)));
+ }
+
Just from a formatting standpoint, drop the open/close curlys, they're
not needed and they're mis-formatted. Dropping them is the easiest fix.
Given the limited testing capabilities for BE on RISC-V, I'd really like
to see at least a scan-asm test as a proxy for an execution test. I
would recommend testing both QI and HI objects.
Jeff
