[Using Ramana’s email listed in MAINTAINERS]
> On 3 Oct 2025, at 11:45, Tamar Christina <[email protected]> wrote:
>
> This patch is a mechanical rewrite of the widen_[us]sum optabs from a direct
> to
> a conversion optab. The result of which requires the output mode to be added
> to
> the existing patterns.
>
> No change in functionality is expected.
>
> Bootstrapped Regtested on arm-none-linux-gnueabihf and no issues.
>
> Ok for master?
>
FWIW this looks ok to me mechanically, but needs approval from the maintainers.
Thanks,
Kyrill
> Thanks,
> Tamar
>
> gcc/ChangeLog:
>
> PR middle-end/122069
> * config/arm/iterators.md (v_double_width): New, matching
> V_double_width.
> * config/arm/neon.md (widen_ssum<mode>3): Renamed ...
> (widen_ssum<v_double_width><mode>3, widen_ssum<V_widen_l><mode>3): ...
> into these.
> (widen_usum<mode>3): Renamed ...
> (widen_usum<v_double_width><mode>3, widen_usum<V_widen_l><mode>3): ...
> into these.
>
> ---
> diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
> index
> 0c163ed4782091699cbbaff71d28ca5b5917d63f..12ec4b530cf0e01a0d6b9c3975f889edad0100ef
> 100644
> --- a/gcc/config/arm/iterators.md
> +++ b/gcc/config/arm/iterators.md
> @@ -1788,6 +1788,11 @@ (define_mode_attr V_double_width [(V8QI "V4HI") (V16QI
> "V8HI")
> (V4HI "V2SI") (V8HI "V4SI")
> (V2SI "DI") (V4SI "V2DI")])
>
> +;; Modes with double-width elements.
> +(define_mode_attr v_double_width [(V8QI "v4hi") (V16QI "v8hi")
> + (V4HI "v2si") (V8HI "v4si")
> + (V2SI "di") (V4SI "v2di")])
> +
> ;; Double-sized modes with the same element size.
> ;; Used for neon_vdup_lane, where the second operand is double-sized
> ;; even when the first one is quad.
> diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
> index
> c887e7fcdff3d2131fe60dd0801b004b46885f3c..4ca15273088894dcc438f054691231a98e5f863b
> 100644
> --- a/gcc/config/arm/neon.md
> +++ b/gcc/config/arm/neon.md
> @@ -981,7 +981,7 @@ (define_insn "neon_load_count"
>
> ;; Widening operations
>
> -(define_expand "widen_ssum<mode>3"
> +(define_expand "widen_ssum<v_double_width><mode>3"
> [(set (match_operand:<V_double_width> 0 "s_register_operand")
> (plus:<V_double_width>
> (sign_extend:<V_double_width>
> @@ -1040,7 +1040,7 @@ (define_insn "vec_sel_widen_ssum_hi<mode><V_half>3"
> }
> [(set_attr "type" "neon_add_widen")])
>
> -(define_insn "widen_ssum<mode>3"
> +(define_insn "widen_ssum<V_widen_l><mode>3"
> [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
> (plus:<V_widen>
> (sign_extend:<V_widen>
> @@ -1051,7 +1051,7 @@ (define_insn "widen_ssum<mode>3"
> [(set_attr "type" "neon_add_widen")]
> )
>
> -(define_expand "widen_usum<mode>3"
> +(define_expand "widen_usum<v_double_width><mode>3"
> [(set (match_operand:<V_double_width> 0 "s_register_operand")
> (plus:<V_double_width>
> (zero_extend:<V_double_width>
> @@ -1110,7 +1110,7 @@ (define_insn "vec_sel_widen_usum_hi<mode><V_half>3"
> }
> [(set_attr "type" "neon_add_widen")])
>
> -(define_insn "widen_usum<mode>3"
> +(define_insn "widen_usum<V_widen_l><mode>3"
> [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
> (plus:<V_widen> (zero_extend:<V_widen>
> (match_operand:VW 1 "s_register_operand" "%w"))
>
>
> --
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 0c163ed4782091699cbbaff71d28ca5b5917d63f..12ec4b530cf0e01a0d6b9c3975f889edad0100ef 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -1788,6 +1788,11 @@ (define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI")
(V4HI "V2SI") (V8HI "V4SI")
(V2SI "DI") (V4SI "V2DI")])
+;; Modes with double-width elements.
+(define_mode_attr v_double_width [(V8QI "v4hi") (V16QI "v8hi")
+ (V4HI "v2si") (V8HI "v4si")
+ (V2SI "di") (V4SI "v2di")])
+
;; Double-sized modes with the same element size.
;; Used for neon_vdup_lane, where the second operand is double-sized
;; even when the first one is quad.
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index c887e7fcdff3d2131fe60dd0801b004b46885f3c..4ca15273088894dcc438f054691231a98e5f863b 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -981,7 +981,7 @@ (define_insn "neon_load_count"
;; Widening operations
-(define_expand "widen_ssum<mode>3"
+(define_expand "widen_ssum<v_double_width><mode>3"
[(set (match_operand:<V_double_width> 0 "s_register_operand")
(plus:<V_double_width>
(sign_extend:<V_double_width>
@@ -1040,7 +1040,7 @@ (define_insn "vec_sel_widen_ssum_hi<mode><V_half>3"
}
[(set_attr "type" "neon_add_widen")])
-(define_insn "widen_ssum<mode>3"
+(define_insn "widen_ssum<V_widen_l><mode>3"
[(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
(plus:<V_widen>
(sign_extend:<V_widen>
@@ -1051,7 +1051,7 @@ (define_insn "widen_ssum<mode>3"
[(set_attr "type" "neon_add_widen")]
)
-(define_expand "widen_usum<mode>3"
+(define_expand "widen_usum<v_double_width><mode>3"
[(set (match_operand:<V_double_width> 0 "s_register_operand")
(plus:<V_double_width>
(zero_extend:<V_double_width>
@@ -1110,7 +1110,7 @@ (define_insn "vec_sel_widen_usum_hi<mode><V_half>3"
}
[(set_attr "type" "neon_add_widen")])
-(define_insn "widen_usum<mode>3"
+(define_insn "widen_usum<V_widen_l><mode>3"
[(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
(plus:<V_widen> (zero_extend:<V_widen>
(match_operand:VW 1 "s_register_operand" "%w"))
